知搜-全球专利检索

  1. 登录
  2. 注册

搜索结果

2931 条记录 (耗时 0.053 秒)

    SINGLE CRYSTAL SILICON CORES FOR STACKED MEMORY CELLS
    1.
    发明公开
    SINGLE CRYSTAL SILICON CORES FOR STACKED MEMORY CELLS 审中-公开

    公开(公告)号：US20240130128A1

    公开(公告)日：2024-04-18

    申请号：US18047571

    申请日：2022-10-18

    申请人： Micron Technology, Inc.

    发明人： Yongjun Hu

    IPC分类号： H01L27/1157 ,  G11C5/06 ,  H01L27/11524 ,  H01L27/11578

    CPC分类号： H01L27/1157 ,  G11C5/063 ,  H01L27/11524 ,  H01L27/11578

    摘要： Methods, systems, and devices for single crystal silicon cores for stacked memory cells are described. A memory device may be formed using silicon cores that are each associated with a set of multiple memory cells. Multiple silicon cores may extend along a first direction, and multiple sleeves of memory materials and conductive materials may be formed around each silicon core. Each sleeve of memory materials may be associated with a respective memory cell and each conductive material may be associated with a word line, such that each silicon core may be associated with multiple memory cells. The respective sleeves of memory materials and conductive materials may be formed from larger sleeves of material that may be etched into sections of the memory materials and the conductive materials along the silicon cores.

    CIRCUITS HAVING ENHANCED ELECTRICAL ISOLATION
    2.
    发明公开
    CIRCUITS HAVING ENHANCED ELECTRICAL ISOLATION 审中-公开

    公开(公告)号：US20240120371A1

    公开(公告)日：2024-04-11

    申请号：US18045528

    申请日：2022-10-11

    申请人： Allegro MicroSystems, LLC

    发明人： James McClay ,  Maxim Klebanov ,  Sundar Chetlur ,  Thomas S. Chung

    IPC分类号： H01L29/06 ,  H01L27/11524 ,  H01L29/788

    CPC分类号： H01L29/0646 ,  H01L27/11524 ,  H01L29/7883

    摘要： Methods and apparatus for a device that includes a circuit, such as a memory cell, and an isolation structure to electrically isolate the circuit cell. The isolation structure can include a p-type substrate, a first series of p-type material extending to the p-type substrate, and a second series of p-type material extending to the p-type substrate. The first series of p-type material, the p-type substrate, and the second series of p-type material surrounds a first side, a second side, and a bottom of the circuit cell to electrically isolate the circuit cell with continuous p-type material. In some embodiments, the first series of p-type material comprises p-type well regions. In some embodiments, the first series of p-type material comprises deep trench isolation.

    Memory Circuitry And Method Used In Forming Memory Circuitry
    4.
    发明公开
    Memory Circuitry And Method Used In Forming Memory Circuitry 审中-公开

    公开(公告)号：US20240071496A1

    公开(公告)日：2024-02-29

    申请号：US17897460

    申请日：2022-08-29

    申请人： Micron Technology, Inc.

    发明人： John D. Hopkins ,  Alyssa N. Scarbrough

    IPC分类号： G11C16/04 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11582

    CPC分类号： G11C16/0483 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11582

    摘要： Memory circuitry comprising strings of memory cells comprises a stack comprising vertically-alternating insulative tiers and conductive tiers. Channel-material strings of memory cells extend through the insulative tiers and the conductive tiers in a memory-array region. The insulative tiers and the conductive tiers extend from the memory-array region into a stair-step region. The stair-step region comprises a cavity comprising a flight of stairs extending along a first direction. Multiple different-depth and height-sequential treads in individual of the stairs extend along a second direction that is orthogonal to the first direction. Individual of the multiple different-depth treads comprise conducting material of one of the conductive tiers. The cavity comprises a pair of laterally-opposing outermost sidewalls relative to the second direction and that individually extend along the first direction. The multiple different-depth and height-sequential treads in the individual stairs comprise a single flight of said treads that extends along the second direction from one of the laterally-opposing outermost sidewalls to the other of the laterally-opposing outermost sidewalls. Methods are disclosed.

    TWO TRANSISTOR MEMORY CELLS WITH SOURCE-DRAIN COUPLING IN ONE TRANSISTOR
    6.
    发明公开
    TWO TRANSISTOR MEMORY CELLS WITH SOURCE-DRAIN COUPLING IN ONE TRANSISTOR 审中-公开

    公开(公告)号：US20230413547A1

    公开(公告)日：2023-12-21

    申请号：US17843867

    申请日：2022-06-17

    申请人： Intel Corporation

    发明人： Sagar Suthram ,  Abhishek A. Sharma ,  Wilfred Gomes ,  Anand S. Murthy ,  Tahir Ghani ,  Pushkar Sharad Ranade

    IPC分类号： H01L27/1156 ,  H01L27/11524

    CPC分类号： H01L27/1156 ,  H01L27/11524

    摘要： IC devices implementing 2T memory cells with source-drain coupling in one transistor, and related assemblies and methods, are disclosed herein. In particular, 2T memory cells presented herein use first and second transistors arranged so that source and drain terminals of the second transistor are coupled to one another. A memory state may be represented by charge indicative of the bit value stored in the second transistor, while the first transistor may serve as a switch to control access to the second transistor. 2T memory cells with source-drain coupling in one transistor provide a promising way to increasing memory cell densities, drive current, and design flexibility in making electrical connections to, or between, various transistor terminals and control lines of memory arrays, thus providing good scalability in the number of 2T memory cells included in memory arrays.

    ACTIVE RESISTOR ARRAY OF SEMICONDUCTOR MEMORY DEVICE
    10.
    发明公开
    ACTIVE RESISTOR ARRAY OF SEMICONDUCTOR MEMORY DEVICE 审中-公开

    公开(公告)号：US20230328977A1

    公开(公告)日：2023-10-12

    申请号：US17883842

    申请日：2022-08-09

    申请人： Samsung Electronics Co., Ltd.

    发明人： Ansoo PARK ,  Ahreum KIM

    IPC分类号： H01L27/11524 ,  H01L27/11519 ,  H01L27/11529 ,  H01L27/08

    CPC分类号： H01L27/11524 ,  H01L27/0802 ,  H01L27/11529 ,  H01L27/11519

    摘要： An active resistor array of a semiconductor memory device comprises a first active resistor in a first active resistor region; a second active resistor in the first active resistor region and arranged in parallel with the first active resistor, and an isolation element layer interposed therebetween; a third active resistor formed in a second active resistor region; a first selection transistor formed in a first selection transistor region and connected to the second active resistor; and a second selection transistor formed in a second selection transistor region and connected to the third active resistor. The first and second selection transistors are connected to the same gate layer. The gate layer of the first and second selection transistors is on the isolation element layer. Since example embodiments may help to ensure the uniformity of the layout pattern, active resistance distribution may be improved due to reduction in process variation.