公开(公告)号：US20240215232A1

公开(公告)日：2024-06-27

申请号：US18428836

申请日：2024-01-31

Applicant: Micron Technology, Inc.

Inventor： Shuangqiang Luo ,  John D. Hopkins ,  Lifang Xu ,  Nancy M. Lomeli ,  Indra V. Chary ,  Kar Wui Thong ,  Shicong Wang

IPC: H10B41/27 ,  G11C5/02 ,  G11C5/06 ,  H01L21/768 ,  H10B41/50 ,  H10B43/27 ,  H10B43/50

CPC classification number: H10B41/27 ,  G11C5/025 ,  G11C5/06 ,  H01L21/768 ,  H10B41/50 ,  H10B43/27 ,  H10B43/50

Abstract: A microelectronic device comprises a stack structure comprising a vertically alternating sequence of conductive material and insulative material arranged in tiers. The stack structure has blocks separated from one another by first dielectric slot structures. Each of the blocks comprises two crest regions, a stadium structure interposed between the two crest regions in a first horizontal direction and comprising opposing staircase structures each having steps comprising edges of the tiers of the stack structure, and two bridge regions neighboring opposing sides of the stadium structure in a second horizontal direction orthogonal to the first horizontal direction and having upper surfaces substantially coplanar with upper surfaces of the two crest regions. At least one second dielectric slot structure is within horizontal boundaries of the stadium structure in the first horizontal direction and partially vertically extends through and segmenting each of the two bridge regions. Memory devices, electronic systems, and methods of forming microelectronic devices are also described.

公开(公告)号：US20240196606A1

公开(公告)日：2024-06-13

申请号：US18513430

申请日：2023-11-17

Applicant: Micron Technology, Inc.

Inventor： Lifang Xu ,  Harsh Narendrakumar Jain ,  Indra V. Chary ,  Richard J. Hill

IPC: H10B41/35 ,  G11C5/02 ,  G11C16/04 ,  H10B41/10 ,  H10B41/20 ,  H10B43/10 ,  H10B43/20 ,  H10B43/35

CPC classification number: H10B41/35 ,  G11C5/025 ,  G11C16/0483 ,  H10B41/10 ,  H10B41/20 ,  H10B43/10 ,  H10B43/20 ,  H10B43/35

Abstract: A microelectronic device includes a stack structure comprising blocks, additional dielectric slot structures, and a further dielectric slot structure. The stack structure includes alternating tiers of conductive and insulative structures. A block comprises a stadium structure and crest regions. The stadium structure includes staircase structures having steps comprising edges of the tiers. The additional dielectric slot structures individually extend in the first direction across a first of the crest regions and at least partially into the stadium structure. The additional dielectric slot structures are separated from one another in a second direction orthogonal to the first direction and individually vertically extend through the tiers. The further dielectric slot structure extends in the second direction across a second of the crest regions. The further dielectric slot structure intersects at least one of the additional dielectric slot structures and vertically extend through the tiers.

公开(公告)号：US20240046989A1

公开(公告)日：2024-02-08

申请号：US17882053

申请日：2022-08-05

Applicant: Micron Technology, Inc.

Inventor： Jiewei Chen ,  Shuangqiang Luo ,  Lifang Xu

IPC: G11C16/04 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11582

CPC classification number: G11C16/0483 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11582

Abstract: A method used in forming a memory array comprising strings of memory cells comprises forming a lower stack comprising vertically-alternating different-composition lower first tiers and lower second tiers. The lower stack comprises lower channel-material strings extending through the lower first tiers and the lower second tiers. An upper stack is formed directly above the lower stack. The upper stack comprises vertically-alternating different-composition upper first tiers and upper second tiers. The upper stack comprises upper channel-material strings of select-gate transistors. Individual of the upper channel-material strings are directly electrically coupled to individual of the lower channel-material strings. The upper and lower first tiers are conductive at least in a finished-circuitry construction. The upper and lower second tiers are insulative and comprise insulative material. An insulator tier comprising insulator material is directly below a lowest of the upper first tiers and directly above an uppermost of the lower first tiers. The insulator material is of different composition from that of the insulative material of the upper second tiers and of different composition from that of the insulative material of the lower second tiers. Other embodiments, including structure, are disclosed.

公开(公告)号：US11856763B2

公开(公告)日：2023-12-26

申请号：US17205954

申请日：2021-03-18

Applicant: Micron Technology, Inc.

Inventor： Lifang Xu ,  Sidhartha Gupta ,  Kar Wui Thong ,  Harsh Narendrakumar Jain

IPC: H10B41/27 ,  H01L29/78 ,  H01L29/66 ,  G11C5/06 ,  H10B43/27

CPC classification number: H10B41/27 ,  G11C5/06 ,  H01L29/66666 ,  H01L29/7827 ,  H10B43/27

Abstract: A method of forming a microelectronic device including a first stack structure comprising alternating levels of insulative structures and other insulative structures, forming strings of memory cells through the first stack structure, forming a second stack structure over the first stack structure, based at least partially on observed amount of pillar bending within the first stack structure, forming a first tailored reticle specific to the observed amount of pillar bending, utilizing the first tailored reticle to form openings extending through the second stack structure and over some of the strings of memory cells, wherein centers of the openings over the strings of memory cells are at least substantially aligned with the centers of uppermost surfaces of the strings of memory cells in a direction of the observed pillar bending, and forming upper pillars extending through the second stack structure and over some of the strings of memory cells.

公开(公告)号：US20230275190A1

公开(公告)日：2023-08-31

申请号：US18310012

申请日：2023-05-01

Applicant: Micron Technology, Inc.

Inventor： Martin F. Schubert ,  Vladimir Odnoblyudov ,  Lifang Xu

IPC: H01L33/38 ,  H01L33/42 ,  H01L33/00 ,  H01L33/40 ,  H01L33/06 ,  H01L33/32 ,  H01L33/50 ,  H01L33/56 ,  H01L33/30

CPC classification number: H01L33/382 ,  H01L33/06 ,  H01L33/30 ,  H01L33/32 ,  H01L33/42 ,  H01L33/56 ,  H01L33/0093 ,  H01L33/0095 ,  H01L33/405 ,  H01L33/502 ,  H01L2933/0016

Abstract: Solid-state radiation transducer (SSRT) devices having buried contacts that are at least partially transparent and associated systems and methods are disclosed herein. An SSRT device configured in accordance with a particular embodiment can include a radiation transducer including a first semiconductor material, a second semiconductor material, and an active region between the first semiconductor material and the second semiconductor material. The SSRT device can further include first and second contacts electrically coupled to the first and second semiconductor materials, respectively. The second contact can include a plurality of buried-contact elements electrically coupled to the second semiconductor material. Individual buried-contact elements can have a transparent portion directly adjacent to the second semiconductor material. The second contact can further include a base portion extending between the buried-contact elements, such as a base portion that is least partially planar and reflective.

公开(公告)号：US20220359398A1

公开(公告)日：2022-11-10

申请号：US17314485

申请日：2021-05-07

Applicant: Micron Technology, Inc.

Inventor： Lingyu Kong ,  Lifang Xu ,  Indra V. Chary ,  Shuangqiang Luo ,  Sok Han Wong

IPC: H01L23/535 ,  H01L23/528 ,  H01L23/00 ,  H01L27/11556 ,  H01L27/11582 ,  H01L21/768

Abstract: A microelectronic device comprises a stack structure comprising insulative structures vertically interleaved with conductive structures, first support pillar structures vertically extending through the stack structure in a first staircase region including steps defined at edges of tiers of the insulative structures and conductive structures, and second support pillar structures vertically extending through the stack structure in a second staircase region including additional steps defined at edges of additional tiers of the insulative structures and conductive structures, the second support pillar structures having a smaller cross-sectional area than the first support pillar structures. Related memory devices, electronic systems, and methods are also described.

公开(公告)号：US20220293631A1

公开(公告)日：2022-09-15

申请号：US17824582

申请日：2022-05-25

Applicant: Micron Technology, Inc.

Inventor： Vinayak Shamanna ,  Lifang Xu ,  Aaron R. Wilson

IPC: H01L27/11582 ,  H01L27/11556 ,  H01L23/528 ,  H01L23/522 ,  H01L23/532 ,  H01L27/11565 ,  H01L21/768 ,  H01L21/02 ,  H01L27/11519

Abstract: Some embodiments include an integrated assembly having a memory array region, a staircase region, and an intervening region between the staircase region and the memory array region. The intervening region includes first and second slabs of insulative material extending through a stack of alternating insulative and conductive levels. Bridging regions are adjacent to the slabs. First slits are along the bridging regions, and second slits extend through the slabs. First panels are within the first slits, and second panels are within the second slits. The second panels are compositionally different from the first panels. Some embodiments include methods of forming integrated assemblies.

公开(公告)号：US11417681B2

公开(公告)日：2022-08-16

申请号：US17215308

申请日：2021-03-29

Applicant: Micron Technology, Inc.

Inventor： Yi Hu ,  Merri L. Carlson ,  Anilkumar Chandolu ,  Indra V. Chary ,  David Daycock ,  Harsh Narendrakumar Jain ,  Matthew J. King ,  Jian Li ,  Brett D. Lowe ,  Prakash Rau Mokhna Rau ,  Lifang Xu

IPC: H01L27/11582 ,  H01L27/11556 ,  H01L27/11565 ,  H01L21/28 ,  H01L21/768 ,  H01L27/115 ,  H01L21/311 ,  H01L21/02 ,  H01L27/11526 ,  H01L27/11519 ,  H01L27/11573 ,  H01L21/3213

Abstract: A method used in forming a memory array comprising strings of memory cells and operative through-array-vias (TAVs) comprises forming a stack comprising vertically-alternating insulative tiers and conductive tiers. The stack comprises a TAV region and an operative memory-cell-string region. The TAV region comprises spaced operative TAV areas. Operative channel-material strings are formed in the stack in the operative memory-cell-string region and dummy channel-material strings are formed in the stack in the TAV region laterally outside of and not within the operative TAV areas. Operative TAVs are formed in individual of the spaced operative TAV areas in the TAV region. Other methods and structure independent of method are disclosed.

公开(公告)号：US20220254727A1

公开(公告)日：2022-08-11

申请号：US17660669

申请日：2022-04-26

Applicant: Micron Technology, Inc.

Inventor： Jordan D. Greenlee ,  Lifang Xu ,  Rita J. Klein ,  Xiao Li ,  Everett A. McTeer

IPC: H01L23/532 ,  H01L23/522 ,  H01L21/768 ,  H01L23/00

Abstract: An apparatus comprising at least one contact structure. The at least one contact structure comprises a contact, an insulating material overlying the contact, and at least one contact via in the insulating material. The at least one contact structure also comprises a dielectric liner material adjacent the insulating material within the contact via, a conductive material adjacent the dielectric liner material, and a stress compensation material adjacent the conductive material and in a central portion of the at least one contact via. The stress compensation material is at least partially surrounded by the conductive material. Memory devices, electronic systems, and methods of forming the apparatus are also disclosed.

公开(公告)号：US11380705B2

公开(公告)日：2022-07-05

申请号：US16784435

申请日：2020-02-07

Applicant: Micron Technology, Inc.

Inventor： Vinayak Shamanna ,  Lifang Xu ,  Aaron R. Wilson

IPC: H01L27/11582 ,  H01L27/11556 ,  H01L23/528 ,  H01L23/522 ,  H01L23/532 ,  H01L27/11565 ,  H01L21/768 ,  H01L21/02 ,  H01L27/11519

Abstract: Some embodiments include an integrated assembly having a memory array region, a staircase region, and an intervening region between the staircase region and the memory array region. The intervening region includes first and second slabs of insulative material extending through a stack of alternating insulative and conductive levels. Bridging regions are adjacent to the slabs. First slits are along the bridging regions, and second slits extend through the slabs. First panels are within the first slits, and second panels are within the second slits. The second panels are compositionally different from the first panels. Some embodiments include methods of forming integrated assemblies.