公开(公告)号：US20240234339A9

公开(公告)日：2024-07-11

申请号：US17972953

申请日：2022-10-25

申请人： MACRONIX International Co., Ltd.

发明人： Cheng-Yu Lee ,  Teng-Hao Yeh

IPC分类号： H01L23/00 ,  H01L23/58 ,  H01L27/11556 ,  H01L27/11582

CPC分类号： H01L23/562 ,  H01L23/564 ,  H01L23/585 ,  H01L27/11556 ,  H01L27/11582

摘要： The present disclosure provides a 3D memory device such as a 3D AND flash memory and a method of forming a seal structure. The 3D memory device includes a chip region including a chip array and a seal region including a seal structure. The seal structure includes a ring-shaped stack structure disposed on a substrate and surrounding the chip array and a dummy channel pillar array penetrating through the ring-shaped stack structure and including a first dummy channel pillar group and a second dummy channel pillar group. The first dummy channel pillar group includes first dummy pillars that are arranged in a first direction and a second direction crossing the first direction to surround the chip array. The second dummy channel pillar group includes second dummy pillars that are arranged in the first direction and the second direction to surround the chip array. The first and the second dummy channel pillars are staggered with each other in the first and second directions.

公开(公告)号：US12029034B2

公开(公告)日：2024-07-02

申请号：US17006656

申请日：2020-08-28

申请人： KIOXIA CORPORATION

发明人： Yasuhito Yoshimizu

IPC分类号： H01L27/11556 ,  H01L23/48 ,  H01L27/11524 ,  H01L27/1157 ,  H01L27/11582 ,  H10B43/27 ,  H10B43/35

CPC分类号： H10B43/27 ,  H01L23/481 ,  H10B43/35

摘要： A semiconductor storage device includes a stacked body, a first columnar portion, a second columnar portion, and second insulating layers. The stacked body includes a plurality of conductive layers and a plurality of first insulating layers alternately stacked in a first direction. The first columnar portion being in a first region, and the second columnar portion being in a second region. The first columnar penetrates the stacked body in the first direction and includes a semiconductor layer. The second columnar portion penetrates the stacked body in the first direction and includes an insulating layer thereon. The second insulating layers are between the second columnar portion and either the conductive layers or the first insulating layers. The insulating layer on the second columnar portion. The second insulating layers are between the insulating layer on the second columnar portion and one of the conductive layers or the first insulating layers.

公开(公告)号：US20240170389A1

公开(公告)日：2024-05-23

申请号：US17991050

申请日：2022-11-21

申请人： YANGTZE MEMORY TECHNOLOGIES CO., LTD.

发明人： Jiajia Wu ,  Bin Yuan ,  Zongke Xu ,  Zhen Guo ,  Beibei Li ,  Xiangning Wang ,  Zhu Yang ,  Qiangwei Zhang ,  Zongliang Huo

IPC分类号： H01L23/522 ,  H01L27/11556 ,  H01L27/11582

CPC分类号： H01L23/5221 ,  H01L27/11556 ,  H01L27/11582

摘要： In certain aspects, a three-dimensional (3D) memory device includes a stack structure including alternating conductive layers and dielectric layers and having at least two core regions and a staircase region between the two core regions, and bridge structures connecting the two core regions and extending through the staircase region in a first direction. A first bridge structure of the bridge structures includes at least two current paths between the two core regions.

公开(公告)号：US20240107760A1

公开(公告)日：2024-03-28

申请号：US17968577

申请日：2022-10-18

申请人： YANGTZE MEMORY TECHNOLOGIES CO., LTD.

发明人： Di Wang ,  Zhong Zhang ,  Wenxi Zhou ,  Zhiliang Xia ,  Zongliang Huo ,  Wei Xie

IPC分类号： H01L27/11582 ,  H01L23/528 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/1157

CPC分类号： H01L27/11582 ,  H01L23/5283 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/1157

摘要： In certain aspects, a three-dimensional (3D) memory device includes channel structures in a first region, word line pick-up structures in a dielectric portion of a second region, and word lines each extending in the first region and a conductive portion of the second region. The first region and the second region are arranged in a first direction. The dielectric portion and the conductive portion of the second region are arranged in a second direction perpendicular to the first direction. The word lines are discontinuous in the dielectric portion of the second region and are electrically connected to the word line pick-up structures, respectively.

公开(公告)号：US20240105623A1

公开(公告)日：2024-03-28

申请号：US17934685

申请日：2022-09-23

申请人： SANDISK TECHNOLOGIES LLC

发明人： Ramy Nashed Bassely SAID ,  Jiahui YUAN ,  Lito De La RAMA

IPC分类号： H01L23/535 ,  H01L23/00 ,  H01L25/00 ,  H01L25/065 ,  H01L25/18 ,  H01L27/11529 ,  H01L27/11556 ,  H01L27/11573 ,  H01L27/11582

CPC分类号： H01L23/535 ,  H01L24/08 ,  H01L24/80 ,  H01L25/0657 ,  H01L25/18 ,  H01L25/50 ,  H01L27/11529 ,  H01L27/11556 ,  H01L27/11573 ,  H01L27/11582 ,  H01L2224/08145 ,  H01L2224/80006 ,  H01L2224/80895 ,  H01L2224/80896 ,  H01L2924/1431 ,  H01L2924/14511

摘要： A memory device includes a horizontal source layer which is laterally separated into laterally isolated portions located in adjacent memory blocks by a dielectric backside trench fill structure or a source isolation dielectric structure.

公开(公告)号：US20240081051A1

公开(公告)日：2024-03-07

申请号：US17901240

申请日：2022-09-01

申请人： Yangtze Memory Technologies Co., Ltd.

发明人： Zhen GUO ,  Wei XU ,  Bin YUAN ,  Chuang MA ,  Jiashi ZHANG ,  ZongLiang HUO

IPC分类号： H01L27/11556 ,  G11C16/04 ,  H01L25/065 ,  H01L27/11524 ,  H01L27/1157 ,  H01L27/11582

CPC分类号： H01L27/11556 ,  G11C16/0483 ,  H01L25/0657 ,  H01L27/11524 ,  H01L27/1157 ,  H01L27/11582

摘要： Aspects of the disclosure provide a semiconductor device. The semiconductor device includes a memory stack of gate layers and insulating layers. The gate layers and the insulating layers are stacked alternatingly and are formed into stair steps in a staircase region. The semiconductor device includes a first landing pad on a first gate layer of a first stair step. The first gate layer is a top gate layer of the first stair step. The semiconductor device further includes a first sidewall isolation structure on a riser sidewall of a second gate layer of a second stair step. The second gate layer is a top gate layer of the second stair step and is stacked on the first gate layer in the memory stack. The first sidewall isolation structure isolates the second gate layer from the first landing pad.

公开(公告)号：US20240074184A1

公开(公告)日：2024-02-29

申请号：US17897976

申请日：2022-08-29

申请人： Micron Technology, Inc.

发明人： Masaaki Higuchi ,  Yoshiaki Fukuzumi ,  Hirokazu Ishigaki

IPC分类号： H01L27/11582 ,  G11C16/04 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/1157

CPC分类号： H01L27/11582 ,  G11C16/0483 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/1157

摘要： An electronic device comprises memory pillars comprising a channel material. The memory pillars extend through both a cell region and a lateral contact region. A portion of the memory pillars in the lateral contact region comprise at least one first step and at least one second step. The electronic device comprises a source contact in direct contact with the channel material in the at least one second step of the portion of the memory pillars in the lateral contact region. Additional electronic devices and methods of forming an electronic device are also disclosed.

公开(公告)号：US20240071498A1

公开(公告)日：2024-02-29

申请号：US17971443

申请日：2022-10-21

申请人： Micron Technology, Inc.

发明人： Yongjun Jeff Hu ,  Pengyuan Zheng

IPC分类号： G11C16/04 ,  H01L23/522 ,  H01L23/528 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11582

CPC分类号： G11C16/0483 ,  H01L23/5226 ,  H01L23/5283 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11582

摘要： A memory array comprising strings of memory cells comprises a conductor tier. The conductor tier comprises upper conductor material directly above and directly against lower conductor material of different composition from that of the upper conductor material. The channel-material strings directly electrically couple to the upper and lower conductor materials of the conductor tier. A through-array-via (TAV) region is included and comprises TAVs. The TAVs individually comprise the upper conductor material, the lower conductor material, and a conducting material that is directly below the conductor tier. The lower conductor material is directly against the upper conductor material and directly against the conducting material. The lower conductor material comprises a metal-rich refractory metal nitride directly above and directly against a non-metal-rich refractory metal nitride that is directly against the conducting material. The lower conductor material may also comprise a first elemental-form metal directly above and directly against a second elemental-form metal that is directly against the conducting material Methods are also disclosed.

公开(公告)号：US20240064978A1

公开(公告)日：2024-02-22

申请号：US17891055

申请日：2022-08-18

申请人： YANGTZE MEMORY TECHNOLOGIES CO., LTD.

发明人： Jingtao Xie ,  Bingjie Yan ,  Kun Zhang ,  Wenxi Zhou ,  Zhiliang Xia ,  Zongliang Huo

IPC分类号： H01L27/11582 ,  H01L27/11556

CPC分类号： H01L27/11582 ,  H01L27/11556

摘要： A three-dimensional (3D) memory device includes a stack, a plurality of contact structures, and a plurality of support structures. The stack in an insulating structure includes a plurality of conductive layers and a plurality of dielectric layers stacked alternatingly, and the stack includes a staircase structure. The plurality of contact structures each extends through the insulating structure and in contact with a respective conductive layer of the plurality of conductive layers in the staircase structure. The plurality of support structures extends through the stack in the staircase structure. Each support structure is in contact with one of the plurality of contact structures.

公开(公告)号：US20240057326A1

公开(公告)日：2024-02-15

申请号：US17887071

申请日：2022-08-12

申请人： Yangtze Memory Technologies Co., Ltd.

发明人： Zhen GUO ,  Wei XU ,  Bin YUAN ,  Li JIANG ,  ZongLiang HUO

IPC分类号： H01L27/11556 ,  H01L27/11524 ,  H01L27/1157 ,  H01L27/11582

CPC分类号： H01L27/11556 ,  H01L27/11524 ,  H01L27/1157 ,  H01L27/11582

摘要： Aspects of the disclosure provide a semiconductor device. The semiconductor device includes a memory stack of gate layers and insulating layers. The gate layers and the insulating layers are stacked alternatingly and are formed into stair steps in a staircase region. Further, the semiconductor device includes a landing stack formed on the stair steps in the staircase region. The landing stack includes an upper layer that is etch selective to a contact isolation layer that covers the staircase region. Then, the semiconductor device includes a first contact structure on a first stair step of the stair steps. The first contact structure extends through a first contact hole in the contact isolation layer and the landing stack. The first contact structure is connected with a first gate layer (e.g., a top gate layer) of the first stair step.