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公开(公告)号：US20240321777A1
公开(公告)日：2024-09-26
申请号：US18735887
申请日：2024-06-06
发明人： Zhong Zhang , Di Wang , Wenxi Zhou
IPC分类号： H01L23/00 , H01L21/768 , H01L23/522 , H01L23/528 , H10B41/27 , H10B43/27
CPC分类号： H01L23/562 , H01L21/76816 , H01L21/76877 , H01L23/5226 , H01L23/5283 , H10B41/27 , H10B43/27
摘要： In certain aspects, a method for forming a three-dimensional (3D) memory device is provided. A stack structure including interleaved first dielectric layers and second dielectric layers is formed. A plurality of channel structures are formed in a first region of the stack structure. A staircase structure is formed in a second region of the stack structure. A first portion of each of the second dielectric layers is replaced with a conductive layer, such that the conductive layer is partially separated between the staircase structure and the plurality of channel structures by a remainder of the second dielectric layer.
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公开(公告)号：US20240298443A1
公开(公告)日：2024-09-05
申请号：US18296161
申请日：2023-04-05
发明人： Zhong Zhang , Di Wang , Wenxi Zhou
摘要： A method of memory device fabrication includes, providing a structure that includes first layers including word lines interleaved respectively with first dielectric layers, second layers including second dielectric layers interleaved respectively with the first dielectric layers, wherein the second layers are adjacent to the first layers, forming vertical recesses each of which extend to a surface of a respective one of the second dielectric layers in a first direction through the second layers, etching a respective lateral recess to expose a surface of a respective one of the word lines, and filling each respective lateral recess with at least one conductive material, such that the at least one conductive material in the respective lateral recess is in contact with the respective one of the word lines through the exposed surface.
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公开(公告)号：US12082408B2
公开(公告)日：2024-09-03
申请号：US17481803
申请日：2021-09-22
发明人： Yuancheng Yang , Wenxi Zhou , Zhiliang Xia , Wei Liu
IPC分类号： H10B41/41 , G11C16/04 , G11C16/10 , G11C16/26 , H01L23/528 , H10B41/27 , H10B41/35 , H10B41/40 , H10B43/27 , H10B43/35 , H10B43/40
CPC分类号： H10B41/41 , G11C16/0483 , G11C16/10 , G11C16/26 , H01L23/5283 , H10B41/27 , H10B41/35 , H10B41/40 , H10B43/27 , H10B43/35 , H10B43/40
摘要： In certain aspects, a three-dimensional (3D) memory device includes a first semiconductor structure, a second semiconductor structure, and a bonding interface between the first and second semiconductor structures. The first semiconductor structure includes an array of NAND memory strings, a first peripheral circuit of the array of NAND memory strings including a first transistor, a polysilicon layer between the array of NAND memory strings and the first peripheral circuit, and a first semiconductor layer in contact with the first transistor. The polysilicon layer is in contact with sources of the array of NAND memory strings. The second semiconductor structure includes a second peripheral circuit of the array of NAND memory strings including a second transistor, and a second semiconductor layer in contact with the second transistor. The second peripheral circuit is between the bonding interface and the second semiconductor layer. The first semiconductor layer is between the polysilicon layer and the second semiconductor layer.
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公开(公告)号：US12075621B2
公开(公告)日：2024-08-27
申请号：US17459480
申请日：2021-08-27
发明人： Yuancheng Yang , Lei Liu , Wenxi Zhou
CPC分类号： H10B43/27 , G11C16/0483 , H10B43/35
摘要： A three-dimensional (3D) memory device includes a doped semiconductor layer, a stack structure, and a channel structure. The stack structure includes interleaved conductive layers and dielectric layers formed on the doped semiconductor layer. The conductive layers include a plurality of word lines, and a drain select gate line. The channel structure extends through the stack structure along a first direction and is in contact with the doped semiconductor layer. The channel structure includes a semiconductor channel, and a memory film over the semiconductor channel. The drain select gate line is in direct contact with the semiconductor channel, each of the plurality of word lines is in direct contact with the memory film, and the drain select gate line and the plurality of word lines include a same material.
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公开(公告)号：US12068250B2
公开(公告)日：2024-08-20
申请号：US17725059
申请日：2022-04-20
发明人： Zhongwang Sun , Zhong Zhang , Wenxi Zhou , Zhiliang Xia
IPC分类号： H01L23/528 , H01L21/311 , H01L21/768 , H01L23/522 , H01L23/535 , H10B41/10 , H10B41/27 , H10B43/10 , H10B43/27 , H10B43/40 , H10B43/50
CPC分类号： H01L23/5283 , H01L21/311 , H01L21/76816 , H01L21/76877 , H01L21/76895 , H01L23/5226 , H01L23/535 , H10B41/10 , H10B41/27 , H10B43/10 , H10B43/27 , H10B43/40 , H10B43/50
摘要： A semiconductor device is provided. The semiconductor device includes a substrate, a stack of word line layers and insulating layers that are stacked alternatingly over the substrate, and channel structures formed in a first array region and a second array region of the stack. The first array region and the second array region are positioned at opposing sides of the stack. A first staircase is formed in a connection region of the stack over the substrate, where the connection region is arranged between the first and second array regions. A second staircase is formed in the connection region of the stack over the substrate, and the connection region in the stack includes a separation region between the first and second staircases.
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公开(公告)号：US12046555B2
公开(公告)日：2024-07-23
申请号：US18484125
申请日：2023-10-10
发明人： Zhongwang Sun , Zhong Zhang , Wenxi Zhou , Zhiliang Xia
IPC分类号： H01L23/528 , H01L21/311 , H01L21/768 , H01L23/522 , H01L23/535 , H10B41/10 , H10B41/27 , H10B43/10 , H10B43/27 , H10B43/40 , H10B43/50
CPC分类号： H01L23/5283 , H01L21/311 , H01L21/76816 , H01L21/76877 , H01L21/76895 , H01L23/5226 , H01L23/535 , H10B41/10 , H10B41/27 , H10B43/10 , H10B43/27 , H10B43/40 , H10B43/50
摘要： In a method for fabricating a semiconductor device, an initial stack of sacrificial word line layers and insulating layers is formed over a substrate of the semiconductor device. The sacrificial word line layers and the insulating layers are disposed over the substrate alternately. A first staircase is formed in a first staircase region of a connection region of the initial stack. A second staircase is formed in a second staircase region of the connection region of the initial stack. The connection region of the initial stack includes a separation region between the first and second staircases, and the connection region is positioned between array regions of the initial stack at opposing sides of the initial stack.
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公开(公告)号：US12033957B2
公开(公告)日：2024-07-09
申请号：US17384116
申请日：2021-07-23
发明人： Zhong Zhang , Di Wang , Wenxi Zhou
IPC分类号： H01L23/00 , H01L21/768 , H01L23/522 , H01L23/528 , H10B41/27 , H10B43/27
CPC分类号： H01L23/562 , H01L21/76816 , H01L21/76877 , H01L23/5226 , H01L23/5283 , H10B41/27 , H10B43/27
摘要： In certain aspects, a three-dimensional (3D) memory device includes a plurality of channel structures in a first region, a staircase structure in a second region, and a word line extending in the first region and the second region. The first region and the second region are arranged along a first direction. The word line is discontinuous in the first direction between the first region and the second region.
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公开(公告)号：US12022656B2
公开(公告)日：2024-06-25
申请号：US17321258
申请日：2021-05-14
发明人： Jianzhong Wu , Kun Zhang , Tingting Zhao , Rui Su , Zhongwang Sun , Wenxi Zhou , Zhiliang Xia
IPC分类号： H10B43/27 , H01L21/768 , H01L23/535 , H10B41/27 , H10B41/35 , H10B43/35
CPC分类号： H10B43/27 , H01L21/76805 , H01L21/76831 , H01L21/7684 , H01L21/76895 , H01L23/535 , H10B41/27 , H10B41/35 , H10B43/35 , H01L2221/1063
摘要： A method for forming a 3D memory device is disclosed. A channel structure extending vertically through a dielectric stack including interleaved sacrificial layers and dielectric layers above a substrate is formed. A sacrificial plug above and in contact with the channel structure is formed. A slit opening extending vertically through the dielectric stack is formed. A memory stack including interleaved conductive layers and the dielectric layers is formed by replacing, through the slit opening, the sacrificial layers with the conductive layers. A first contact portion is formed in the slit opening. The sacrificial plug is removed after forming the first contact portion to expose the channel structure. A channel local contact above and in contact with the channel structure, and a second contact portion above the first contact portion in the slit opening are simultaneously formed.
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公开(公告)号：US20240206148A1
公开(公告)日：2024-06-20
申请号：US18089472
申请日：2022-12-27
发明人： Kun Zhang , Yuancheng Yang , Dongxue Zhao , Tao Yang , Lei Liu , Di Wang , Wenxi Zhou , Zhiliang Xia , Zongliang Huo
IPC分类号： H10B12/00 , H01L23/00 , H01L25/00 , H01L25/065 , H01L25/18
CPC分类号： H01L27/10802 , H01L24/08 , H01L24/80 , H01L25/0657 , H01L25/18 , H01L25/50 , H01L2224/08145 , H01L2224/80895 , H01L2224/80896 , H01L2924/1431 , H01L2924/1436
摘要： A memory device includes a first semiconductor layer, a first memory array, a second memory array, and a first peripheral circuit. The first memory array is disposed on a first side of the first semiconductor layer. The first memory array includes first memory cells, and first split structures. The second memory array is disposed on a second side of the first semiconductor layer opposite to the first side. The second memory array includes second memory cells, and second split structures. The first peripheral circuit including a first peripheral device disposed on the first memory array.
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公开(公告)号：US11839083B2
公开(公告)日：2023-12-05
申请号：US17451884
申请日：2021-10-22
发明人： Yingjie Ouyang , Zhiliang Xia , Lei Jin , Qiguang Wang , Wenxi Zhou , Zhongwang Sun , Rui Su , Yueqiang Pu , Jiwei Cheng
IPC分类号： H10B43/27 , G11C5/06 , H01L23/522 , H01L23/528 , H10B43/10 , H10B43/35
CPC分类号： H10B43/27 , G11C5/063 , H01L23/5226 , H01L23/5283 , H10B43/10 , H10B43/35
摘要： In a method for forming a semiconductor device, a channel structure is formed that extends from a side of a substrate, where the channel structure includes sidewalls and a bottom region. The channel structure further includes a bottom channel contact that is positioned at the bottom region and a channel layer that is formed along the sidewalls and over the bottom channel contact. A high-k layer is formed over the channel layer along the sidewalls of the channel structure and over the bottom channel contact.
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