公开(公告)号：US20240365680A1

公开(公告)日：2024-10-31

申请号：US18764426

申请日：2024-07-05

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Mauricio Manfrini

IPC分类号： H10N50/80 ,  H01L23/522 ,  H10B61/00 ,  H10N50/01 ,  H10N50/10

CPC分类号： H10N50/80 ,  H01L23/5226 ,  H10B61/00 ,  H10N50/01 ,  H10N50/10

摘要： The present disclosure relates to an integrated chip including a bottom electrode arranged within a dielectric layer. A memory element is directly over the bottom electrode and is arranged within the dielectric layer. A top electrode is directly over the memory element and is arranged within the dielectric layer. A conductive via is directly over the top electrode. A pair of lines that extend along opposing sidewalls of the top electrode are directly over, and intersect, an uppermost surface of the memory element. The pair of lines are directly under, and intersect, a lowermost surface of the via.

公开(公告)号：US20240363709A1

公开(公告)日：2024-10-31

申请号：US18770563

申请日：2024-07-11

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Lin-Yu Huang ,  Li-Zhen Yu ,  Chia-Hao Chang ,  Cheng-Chi Chuang ,  Kuan-Lun Cheng ,  Chih-Hao Wang

IPC分类号： H01L29/417 ,  H01L21/768 ,  H01L23/522 ,  H01L29/08 ,  H01L29/78

CPC分类号： H01L29/41791 ,  H01L21/76877 ,  H01L23/5226 ,  H01L29/0847 ,  H01L29/785

摘要： A semiconductor structure includes a substrate; a first structure over the substrate and having a first gate stack and two first gate spacers on two opposing sidewalls of the first gate stack; a second structure over the substrate and having a second gate stack and two second gate spacers on two opposing sidewalls of the second gate stack; a source/drain (S/D) feature over the substrate and adjacent to the first and the second gate stacks; an S/D contact over the S/D feature and between one of the first gate spacers and one of the second gate spacers; a conductive via disposed over and electrically connected to the S/D contact; and a dielectric liner layer. A first portion of the dielectric liner layer is disposed on a sidewall of the one of the first gate spacers and is directly above the S/D contact and spaced from the S/D contact.

公开(公告)号：US20240363569A1

公开(公告)日：2024-10-31

申请号：US18763481

申请日：2024-07-03

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Ting-Li Yang ,  Po-Hao Tsai ,  Ching-Wen Hsiao ,  Hong-Seng Shue ,  Ming-Da Cheng

IPC分类号： H01L23/00 ,  H01L21/768 ,  H01L23/522 ,  H01L23/528

CPC分类号： H01L24/11 ,  H01L21/76816 ,  H01L23/5223 ,  H01L23/5226 ,  H01L23/5283 ,  H01L24/16 ,  H01L2224/11019 ,  H01L2224/13008 ,  H01L2924/19041

摘要： A method of forming a semiconductor device includes: forming an interconnect structure over a substrate; forming a first passivation layer over the interconnect structure; forming a first conductive feature over the first passivation layer and electrically coupled to the interconnect structure; conformally forming a second passivation layer over the first conductive feature and the first passivation layer; forming a dielectric layer over the second passivation layer; and forming a first bump via and a first conductive bump over and electrically coupled to the first conductive feature, where the first bump via is between the first conductive bump and the first conductive feature, where the first bump via extends into the dielectric layer, through the second passivation layer, and contacts the first conductive feature, where the first conductive bump is over the dielectric layer and electrically coupled to the first bump via.

公开(公告)号：US20240363538A1

公开(公告)日：2024-10-31

申请号：US18768002

申请日：2024-07-10

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.

发明人： SHU-WEI LI ,  YU-CHEN CHAN ,  MENG-PEI LU ,  SHIN-YI YANG ,  MING-HAN LEE

IPC分类号： H01L23/532 ,  H01L21/768 ,  H01L23/522

CPC分类号： H01L23/53276 ,  H01L21/76805 ,  H01L21/76877 ,  H01L23/5226 ,  H01L23/53257 ,  H01L23/53271 ,  H01L23/5328

摘要： A semiconductor structure and method of manufacturing a semiconductor structure are provided. The semiconductor structure comprises at least one two-dimensional (2D) conductive structure; a dielectric structure disposed on the 2D conductive structure; and at least one interconnect structure disposed in the dielectric layer and extending into the 2D conductive structure. The interconnect structure laterally contacts the 2D conductive structure.

公开(公告)号：US20240363486A1

公开(公告)日：2024-10-31

申请号：US18771548

申请日：2024-07-12

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Yuan Sheng Chiu ,  Chih-Kai Cheng ,  Tsung-Shu Lin

IPC分类号： H01L23/40 ,  H01L21/48 ,  H01L21/56 ,  H01L23/00 ,  H01L23/31 ,  H01L23/522 ,  H01L23/528

CPC分类号： H01L23/4006 ,  H01L21/4882 ,  H01L21/563 ,  H01L23/3121 ,  H01L23/3171 ,  H01L23/5226 ,  H01L23/5283 ,  H01L24/09 ,  H01L24/17 ,  H01L24/94 ,  H01L2023/405 ,  H01L2023/4087 ,  H01L2224/0231 ,  H01L2224/02373 ,  H01L2224/02379 ,  H01L2224/02381 ,  H01L2224/0401 ,  H01L2224/26155 ,  H01L2224/83897

摘要： In an embodiment, a device includes: an integrated circuit die; a redistribution structure over a front-side surface of the integrated circuit die; a socket over the redistribution structure; a mechanical brace over the socket, the mechanical brace having an opening exposing the socket, edge regions of the socket overlapping edge regions of the mechanical brace at the opening; a first standoff screw disposed in the edge regions of the mechanical brace, the first standoff screw physically contacting the socket, the first standoff screw extending a first distance between the socket and the mechanical brace; and a bolt extending through the mechanical brace and the redistribution structure.

公开(公告)号：US20240363403A1

公开(公告)日：2024-10-31

申请号：US18766300

申请日：2024-07-08

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Chia-Pang Kuo ,  Ya-Lien Lee ,  Chieh-Yi Shen

IPC分类号： H01L21/768 ,  H01L23/522 ,  H01L23/532

CPC分类号： H01L21/76844 ,  H01L21/7681 ,  H01L21/76879 ,  H01L23/5226 ,  H01L23/53238

摘要： A method of forming an integrated circuit structure includes forming an etch stop layer over a conductive feature, forming a dielectric layer over the etch stop layer, forming an opening in the dielectric layer to reveal the etch stop layer, and etching the etch stop layer through the opening using an etchant comprising an inhibitor. An inhibitor film comprising the inhibitor is formed on the conductive feature. The method further includes depositing a conductive barrier layer extending into the opening, performing a treatment to remove the inhibitor film after the conductive barrier layer is deposited, and depositing a conductive material to fill a remaining portion of the opening.

公开(公告)号：US20240362394A1

公开(公告)日：2024-10-31

申请号：US18768895

申请日：2024-07-10

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

发明人： Jung-Chan YANG ,  Ting-Wei CHIANG ,  Cheng-I HUANG ,  Hui-Zhong ZHUANG ,  Chi-Yu LU ,  Stefan RUSU

IPC分类号： G06F30/394 ,  H01L21/76 ,  H01L23/522 ,  H01L23/528 ,  H03K19/094

CPC分类号： G06F30/394 ,  H01L21/76 ,  H01L23/528 ,  H01L23/5286 ,  H03K19/094 ,  H01L23/5226 ,  H01L2924/0002

摘要： An integrated circuit structure includes a first and second power rail on a first level, a first and second set of conductive structures on a second level and a first, second and third conductive structure on a third level. The first set of conductive structures is over the first power rail. The second set of conductive structures is over the second power rail. The first conductive structure overlaps a first conductive structure of the first set of conductive structures and a first conductive structure of the second set of conductive structures. The second conductive structure overlaps a second conductive structure of the first set of conductive structures and a second conductive structure of the second set of conductive structures. The third conductive structure overlaps a third conductive structure of the first set of conductive structures and a third conductive structure of the second set of conductive structures.

公开(公告)号：US12131994B2

公开(公告)日：2024-10-29

申请号：US18362044

申请日：2023-07-31

申请人： GlobalFoundries U.S. Inc.

发明人： Ruilong Xie ,  Lars Liebmann ,  Daniel Chanemougame ,  Geng Han

IPC分类号： H01L23/528 ,  H01L21/768 ,  H01L23/522 ,  H01L23/532 ,  H01L21/02 ,  H01L21/8234 ,  H01L21/8238 ,  H01L27/088 ,  H01L27/092 ,  H01L29/40

CPC分类号： H01L23/5283 ,  H01L21/76802 ,  H01L21/76816 ,  H01L23/5226 ,  H01L23/53295 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/76814 ,  H01L21/76832 ,  H01L21/76835 ,  H01L21/76861 ,  H01L21/76877 ,  H01L21/76879 ,  H01L21/823431 ,  H01L21/823821 ,  H01L27/0886 ,  H01L27/0924 ,  H01L29/401

摘要： An integrated circuit product includes a first layer of insulating material above a device layer of a semiconductor substrate and with a lowermost surface above an uppermost surface of a gate of a transistor in a device layer of the semiconductor substrate. A metallization blocking structure is in an opening in the first layer of insulating material and has a lowermost surface above the uppermost surface of the gate and includes a second insulating material that is different from the first insulating material. A metallization trench is in the first layer of insulating material on opposite sides of the metallization blocking structure. A contact structure is in the second insulating material and entirely below the metallization trench. A conductive metallization line includes first and second portions positioned in the metallization trench on opposite sides of the metallization blocking structure and a long axis extending along the first and second portions.

公开(公告)号：US12131915B2

公开(公告)日：2024-10-29

申请号：US18325905

申请日：2023-05-30

申请人： Taiwan Semiconductor Manufacturing Company Limited

发明人： Jheng-Hong Jiang ,  Chia-Wei Liu ,  Shing-Huang Wu

IPC分类号： H01L21/321 ,  C22C21/12 ,  H01L21/768 ,  H01L23/522 ,  H01L23/532

CPC分类号： H01L21/3212 ,  C22C21/12 ,  H01L21/76802 ,  H01L21/7684 ,  H01L21/76843 ,  H01L21/76877 ,  H01L23/5226 ,  H01L23/53219 ,  H01L23/53223

摘要： A cavity may be formed in a dielectric material layer overlying a substrate. A layer stack including a metallic barrier liner, a metallic fill material layer, and a metallic capping material may be deposited in the cavity and over the dielectric material layer. Portions of the layer stack located above a horizontal plane including a top surface of the dielectric material layer may be removed. A contiguous set of remaining material portions of the layer stack includes a metal interconnect structure that is free of a pitted surface.

公开(公告)号：US20240357826A1

公开(公告)日：2024-10-24

申请号：US18757483

申请日：2024-06-27

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Chao-I Wu ,  Yu-Ming Lin ,  Sai-Hooi Yeong ,  Han-Jong Chia

IPC分类号： H10B51/10 ,  H01L21/28 ,  H01L23/522 ,  H01L29/51 ,  H01L29/66 ,  H01L29/78 ,  H10B51/20 ,  H10B51/30

CPC分类号： H10B51/10 ,  H01L23/5226 ,  H01L29/40111 ,  H01L29/516 ,  H01L29/66666 ,  H01L29/78391 ,  H10B51/20 ,  H10B51/30

摘要： Provided are a memory device and a method of forming the same. The memory device includes a first tier on a substrate and a second tier on the first tier. The first tier includes a first layer stack; a first gate electrode penetrating through the first layer stack; a first channel layer between the first layer stack and the first gate electrode; and a first ferroelectric layer between the first channel layer and the first gate electrode. The second tier includes a second layer stack; a second gate electrode penetrating through the second layer stack; a second channel layer between the second layer stack and the second gate electrode; and a second ferroelectric layer between the second channel layer and the second gate electrode.