-
公开(公告)号：US20240365676A1
公开(公告)日：2024-10-31
申请号：US18770678
申请日：2024-07-12
发明人： YA-LING LEE , TSANN LIN , HAN-JONG CHIA
CPC分类号： H10N50/10 , G01R33/093 , G01R33/098 , G11C11/161 , H10B61/00 , H10N50/01 , H10N50/80 , H10N50/85
摘要： A magnetic tunnel junction (MTJ) element is provided. The MTJ element includes a hard bias layer, a reference layer disposed over the hard bias layer, a tunnel barrier layer disposed over the reference layer, a free layer disposed over the tunnel barrier layer, and a diffusion barrier layer disposed over the free layer wherein the diffusion barrier layer comprises an amorphous and nonmagnetic film of a form X-Z, where X is Fe or Co and Z is Hf, Y, or Zr. The MTJ element in accordance with the present disclosure exhibits a low resistance desired for a low-power write operation, and a high TMR coefficient desired for a low bit-error-rate (BER) read operation.
-
公开(公告)号：US20240365564A1
公开(公告)日：2024-10-31
申请号：US18768995
申请日：2024-07-10
发明人： Chih-Fan Huang , Wen-Chiung Tu , Liang-Wei Wang , Dian-Hau Chen , Yen-Ming Chen
摘要： Semiconductor device and methods of forming the same are provided. A semiconductor device according to one embodiment includes a first source/drain feature and a second source/drain feature, a first metal line disposed in a first dielectric layer and electrically connected to the first source/drain feature, a second metal line disposed in the first dielectric layer and electrically connected to the second source/drain feature, and a first memory element disposed over the first dielectric layer and electrically connected to the first source/drain feature by way of the first metal line. A width of the first metal line is different from a width of the second metal line. By changing the widths of the first metal line and the second metal line, a source line series resistance of a semiconductor device can be advantageously reduced without changing a pitch of two metal lines.
-
公开(公告)号：US12133470B2
公开(公告)日：2024-10-29
申请号：US18059073
申请日：2022-11-28
摘要： The present disclosure provides a semiconductor structure, including an Nth metal layer over a transistor region, where N is a natural number, and a bottom electrode over the Nth metal layer. The bottom electrode comprises a bottom portion having a first width, disposed in a bottom electrode via (BEVA), the first width being measured at a top surface of the BEVA, and an upper portion having a second width, disposed over the bottom portion. The semiconductor structure also includes a magnetic tunneling junction (MTJ) layer having a third width, disposed over the upper portion, a top electrode over the MTJ layer and an (N+1)th metal layer over the top electrode. The first width is greater than the third width.
-
公开(公告)号：US20240357943A1
公开(公告)日：2024-10-24
申请号：US18760005
申请日：2024-06-30
发明人： Chiu-Jung Chiu , Ya-Sheng Feng , I-Ming Tseng , Yi-An Shih , Yu-Chun Chen , Yi-Hui Lee , Chung-Liang Chu , Hsiu-Hao Hu
摘要： A method for fabricating semiconductor device includes the steps of forming an inter-metal dielectric (IMD) layer on a substrate, forming a trench in the IMD layer, forming a synthetic antiferromagnetic (SAF) layer in the trench, forming a metal layer on the SAF layer, planarizing the metal layer and the SAF layer to form a metal interconnection, and forming a magnetic tunneling junction (MTJ) on the metal interconnection.
-
公开(公告)号：US12127483B2
公开(公告)日：2024-10-22
申请号：US17388484
申请日：2021-07-29
发明人： Bi-Shen Lee , Hai-Dang Trinh , Hsun-Chung Kuang , Cheng-Yuan Tsai
摘要： Various embodiments of the present disclosure are directed towards an integrated circuit (IC) chip comprising a memory cell with a sidewall spacer, and/or an etch stop layer, doped to reduce charge accumulation at an interface between the sidewall spacer and the etch stop layer. The memory cell comprises a bottom electrode, a data storage element overlying the bottom electrode, and a top electrode overlying the data storage element. The sidewall spacer overlies the bottom electrode on a common sidewall formed by the data storage element and the top electrode, and the etch stop layer lines the sidewall spacer. The sidewall spacer and the etch stop layer directly contact at the interface and form an electric dipole at the interface. The doping to reduce charge accumulation reduces an electric field produced by the electric dipole, thereby reducing the effect of the electric field on the memory cell.
-
公开(公告)号：US20240349622A1
公开(公告)日：2024-10-17
申请号：US18218926
申请日：2023-07-06
发明人： Jaewoo Jeong , Tiar Ikhtiar , Panagiotis Charilaos Filippou , Chirag Garg , Mahesh Govind Samant
摘要： A magnetic memory device includes a substrate, a seed layer above the substrate, a chemical templating layer above the seed layer, and a first magnetic layer above the chemical templating layer. The seed layer includes ScxN, MnxN, or MgO substantially oriented in (001) direction. The chemical templating layer includes a binary alloy having a Cu3Au prototype structure or a BiF3 prototype structure. The first magnetic layer includes a Heusler compound having perpendicular magnetic anisotropy.
-
7.发明公开公开(公告)号：US20240349514A1
公开(公告)日：2024-10-17
申请号：US18753077
申请日：2024-06-25
发明人： Yong-Jie WU , Yen-Chung HO , Hui-Hsien WEI , Chia-Jung YU , Pin-Cheng HSU , Mauricio MANFRINI , Chung-Te LIN
IPC分类号： H10B61/00 , H01L21/02 , H01L29/24 , H01L29/417 , H01L29/66 , H01L29/78 , H10B53/30 , H10B63/00 , H10N50/01 , H10N70/00
CPC分类号： H10B61/22 , H01L21/02565 , H01L29/24 , H01L29/41791 , H01L29/66969 , H01L29/785 , H10B53/30 , H10B63/30 , H10N50/01 , H10N70/011
摘要： A semiconductor device includes a semiconducting metal oxide fin located over a lower-level dielectric material layer, a gate dielectric layer located on a top surface and sidewalls of the semiconducting metal oxide fin, a gate electrode located on the gate dielectric layer and straddling the semiconducting metal oxide fin, an access-level dielectric material layer embedding the gate electrode and the semiconducting metal oxide fin, a memory cell embedded in a memory-level dielectric material layer and including a first electrode, a memory element, and a second electrode, and a bit line overlying the memory cell. The first electrode may be electrically connected to a drain region within the semiconducting metal oxide fin through a first electrically conductive path, and the second electrode is electrically connected to the bit line.
-
公开(公告)号：US20240341198A1
公开(公告)日：2024-10-10
申请号：US18292218
申请日：2022-07-25
申请人： SHIN-ETSU CHEMICAL CO., LTD. , NATIONAL UNIVERSITY CORPORATION TOYOHASHI UNIVERSITY OF TECHNOLOGY
发明人： Toshiaki WATANABE , Mitsuteru INOUE , Taichi GOTO
摘要： A method for manufacturing a spin wave excitation/detection structure to excite and detect a spin wave. The method includes: forming an insulating magnetic film on a donor substrate, producing a bonded substrate by bonding a surface of the insulating magnetic film on the donor substrate to a surface of a support substrate via a conductive film, removing the donor substrate from the bonded substrate, and forming a conductive line on the insulating magnetic film. The spin wave excitation/detection structure includes the support substrate, the conductive film provided on the support substrate, the insulating magnetic film provided on the conductive film, and the conductive line provided on the insulating magnetic film. This provides the method that can manufacture the spin wave excitation/detection structure, having a structure with high strength, the spin wave that can be excited with high intensity, and the spin wave that can be excited with broad frequency bandwidth.
-
公开(公告)号：US12114511B2
公开(公告)日：2024-10-08
申请号：US17462577
申请日：2021-08-31
发明人： Hui-Hsien Wei , Yen-Chung Ho , Chia-Jung Yu , Yong-Jie Wu , Pin-Cheng Hsu
摘要： A semiconductor device, an integrated circuit, and a method of manufacturing the same are provided. The semiconductor device includes a substrate, a thin-film transistor (TFT) over the substrate, and a magnetoresistive random-access memory (MRAM) cell electrically coupled to the TFT. The TFT includes a gate electrode; a gate dielectric layer disposed over the gate electrode; source/drain electrodes disposed above the gate electrode; and an active layer disposed above the gate electrode. A protection layer is disposed between the TFT and the MRAM cell and electrically connects the MRAM cell to the TFT.
-
公开(公告)号：US12108685B2
公开(公告)日：2024-10-01
申请号：US17479668
申请日：2021-09-20
摘要： A semiconductor structure comprises a reference layer of a magnetic random-access memory pillar structure, the reference layer having a first diameter, a free layer of the magnetic random-access memory pillar structure disposed over the reference layer, the free layer having a second diameter, and an electrode layer of the magnetic random-access memory pillar structure disposed over the free layer, the electrode layer having a third diameter. At least two of the first diameter, the second diameter and the third diameter are different.
-
-
-
-
-
-
-
-
-
搜索结果
669 条记录 (耗时 0.019 秒)
