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公开(公告)号:US20220093616A1
公开(公告)日:2022-03-24
申请号:US17368869
申请日:2021-07-07
发明人: Hui-Hsien WEI , Yen-Chung HO , Chia-Jung YU , Yong-Jie WU , Pin-Cheng HSU
IPC分类号: H01L27/11507 , H01L29/417 , H01L29/786 , H01L29/78
摘要: A planar insulating spacer layer can be formed over a substrate, and a combination of a semiconducting material layer, a thin film transistor (TFT) gate dielectric layer, and a gate electrode can be formed over the planar insulating spacer layer. A dielectric matrix layer is formed thereabove. A source-side via cavity and a drain-side via cavity can be formed through the dielectric matrix layer over end portions of the semiconducting material layer. Mechanical stress can be generated between the end portions of the semiconducting material layer by changing a lattice constant of end portions of the semiconducting material layer. The mechanical stress can enhance the mobility of charge carriers in a channel portion of the semiconducting material layer.
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2.
公开(公告)号:US20210399051A1
公开(公告)日:2021-12-23
申请号:US16909109
申请日:2020-06-23
发明人: Yong-Jie WU , Yen-Chung HO , Pin-Cheng HSU , Mauricio MANFRINI , Chung-Te LIN
IPC分类号: H01L27/24 , H01L45/00 , H01L29/786 , H01L29/66 , H01L27/11507 , H01L27/11509
摘要: A device structure includes at least one selector device. Each selector device includes a vertical stack including, from bottom to top, a bottom electrode, a metal oxide semiconductor channel layer, and a top electrode and located over a substrate, a gate dielectric layer contacting sidewalls of the bottom electrode, the metal oxide semiconductor channel layer, and the top electrode, and a gate electrode formed within the gate dielectric layer and having a top surface that is coplanar with a top surface of the top electrode. Each top electrode or each bottom electrode of the at least one selector device may be contacted by a respective nonvolatile memory element to provide a one-selector one-resistor memory cell.
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公开(公告)号:US20220344202A1
公开(公告)日:2022-10-27
申请号:US17523111
申请日:2021-11-10
发明人: Yong-Jie WU , Yen-Chung HO , Hui-Hsien WEI , Chia-Jung YU , Pin-Cheng HSU , Feng-Cheng YANG , Chung-Te LIN
IPC分类号: H01L21/768 , H01L23/528 , H01L29/66 , H01L29/40
摘要: A disclosed method of fabricating a semiconductor structure includes forming a first conductive pattern over a substrate, with the first conductive pattern including a first conductive line and a second conductive line. A barrier layer may be conformally formed over the first conductive line and the second conductive line of the first conductive pattern. An insulating layer may be formed over the barrier layer. The insulating layer may be patterned to form openings between conductive lines of the first conductive pattern a second conductive pattern may be formed in the openings. The second conductive pattern may include a third conductive line is physically separated from the first conductive pattern by the barrier layer. The presence of the barrier layer reduces the risk of a short circuit forming between the first and second conductive patterns. In this sense, the second conductive pattern may be self-aligned relative to the first conductive pattern.
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公开(公告)号:US20210399046A1
公开(公告)日:2021-12-23
申请号:US17227541
申请日:2021-04-12
发明人: Yong-Jie WU , Yen-Chung HO , Hui-Hsien WEI , Chia-Jung YU , Pin-Cheng HSU , Mauricio MANFRINI , Chung-Te LIN
IPC分类号: H01L27/22 , H01L43/02 , H01L43/12 , H01L29/24 , H01L29/423 , H01L29/786 , H01L21/02 , H01L29/66
摘要: A memory structure, device, and method of making the same, the memory structure including a surrounding gate thin film transistor (TFT) and a memory cell stacked on the GAA transistor. The GAA transistor includes: a channel comprising a semiconductor material; a source electrode electrically connected to a first end of the channel; a drain electrode electrically connected to an opposing second end of the channel; a high-k dielectric layer surrounding the channel; and a gate electrode surrounding the high-k dielectric layer. The memory cell includes a first electrode that is electrically connected to the drain electrode.
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5.
公开(公告)号:US20240349514A1
公开(公告)日:2024-10-17
申请号:US18753077
申请日:2024-06-25
发明人: Yong-Jie WU , Yen-Chung HO , Hui-Hsien WEI , Chia-Jung YU , Pin-Cheng HSU , Mauricio MANFRINI , Chung-Te LIN
IPC分类号: H10B61/00 , H01L21/02 , H01L29/24 , H01L29/417 , H01L29/66 , H01L29/78 , H10B53/30 , H10B63/00 , H10N50/01 , H10N70/00
CPC分类号: H10B61/22 , H01L21/02565 , H01L29/24 , H01L29/41791 , H01L29/66969 , H01L29/785 , H10B53/30 , H10B63/30 , H10N50/01 , H10N70/011
摘要: A semiconductor device includes a semiconducting metal oxide fin located over a lower-level dielectric material layer, a gate dielectric layer located on a top surface and sidewalls of the semiconducting metal oxide fin, a gate electrode located on the gate dielectric layer and straddling the semiconducting metal oxide fin, an access-level dielectric material layer embedding the gate electrode and the semiconducting metal oxide fin, a memory cell embedded in a memory-level dielectric material layer and including a first electrode, a memory element, and a second electrode, and a bit line overlying the memory cell. The first electrode may be electrically connected to a drain region within the semiconducting metal oxide fin through a first electrically conductive path, and the second electrode is electrically connected to the bit line.
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6.
公开(公告)号:US20230389333A1
公开(公告)日:2023-11-30
申请号:US18446755
申请日:2023-08-09
发明人: Hui-Hsien WEI , Yen-Chung HO , Chia-Jung YU , Yong-Jie WU , Pin-Cheng HSU
IPC分类号: H10B53/30 , H01L29/78 , H01L29/786 , H01L29/417
CPC分类号: H10B53/30 , H01L29/7845 , H01L29/78618 , H01L29/41733
摘要: A planar insulating spacer layer can be formed over a substrate, and a combination of a semiconducting material layer, a thin film transistor (TFT) gate dielectric layer, and a gate electrode can be formed over the planar insulating spacer layer. A dielectric matrix layer is formed thereabove. A source-side via cavity and a drain-side via cavity can be formed through the dielectric matrix layer over end portions of the semiconducting material layer. Mechanical stress can be generated between the end portions of the semiconducting material layer by changing a lattice constant of end portions of the semiconducting material layer. The mechanical stress can enhance the mobility of charge carriers in a channel portion of the semiconducting material layer.
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公开(公告)号:US20230380186A1
公开(公告)日:2023-11-23
申请号:US18230846
申请日:2023-08-07
发明人: Yong-Jie WU , Yen-Chung HO , Hui-Hsien WEI , Chia-Jung YU , Pin-Cheng HSU , Mauricio MANFRINI , Chung-Te LIN
IPC分类号: H10B61/00 , H01L29/24 , H01L29/66 , H01L29/786 , H01L21/02 , H10B53/30 , H10B63/00 , H10N50/01 , H10N70/00
CPC分类号: H10B61/22 , H01L29/24 , H01L29/66969 , H01L29/7869 , H01L21/02565 , H01L29/78645 , H10B53/30 , H10B63/30 , H10N50/01 , H10N70/063
摘要: A memory structure includes: first and second word lines; a high-k dielectric layer disposed on the first and second word lines; a channel layer disposed on the high-k dielectric layer and comprising a semiconductor material; first and second source electrodes electrically contacting the channel layer; a first drain electrode disposed on the channel layer between the first and second source electrodes; a memory cell electrically connected to the first drain electrode; and a bit line electrically connected to the memory cell.
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8.
公开(公告)号:US20230371278A1
公开(公告)日:2023-11-16
申请号:US18358460
申请日:2023-07-25
发明人: Yong-Jie WU , Yen-Chung HO , Hui-Hsien WEI , Chia-Jung YU , Pin-Cheng HSU , Mauricio MANFRINI , Chung-Te LIN
IPC分类号: H01L29/78 , H01L29/24 , H01L21/02 , H01L29/66 , H01L29/417
CPC分类号: H10B61/22 , H01L29/24 , H01L29/785 , H01L21/02565 , H10B53/30 , H10B63/30 , H10N70/011 , H01L29/66969 , H01L29/41791 , H10N50/01
摘要: A semiconductor device includes a semiconducting metal oxide fin located over a lower-level dielectric material layer, a gate dielectric layer located on a top surface and sidewalls of the semiconducting metal oxide fin, a gate electrode located on the gate dielectric layer and straddling the semiconducting metal oxide fin, an access-level dielectric material layer embedding the gate electrode and the semiconducting metal oxide fin, a memory cell embedded in a memory-level dielectric material layer and including a first electrode, a memory element, and a second electrode, and a bit line overlying the memory cell. The first electrode may be electrically connected to a drain region within the semiconducting metal oxide fin through a first electrically conductive path, and the second electrode is electrically connected to the bit line.
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9.
公开(公告)号:US20220344504A1
公开(公告)日:2022-10-27
申请号:US17523076
申请日:2021-11-10
发明人: Yong-Jie WU , Yen-Chung HO , Hui-Hsien WEI , Chia-Jung YU , Pin-Cheng HSU , Feng-Cheng YANG , Chung-Te LIN
IPC分类号: H01L29/786 , H01L29/423 , H01L29/417 , H01L29/45 , H01L29/49
摘要: A disclosed semiconductor device includes a substrate, a gate electrode formed on the substrate, a gate dielectric layer formed over the gate electrode, a source electrode located adjacent to a first side of the gate electrode, and a drain electrode located adjacent to a second side of the gate electrode. A gate dielectric formed from an etch-stop layer and/or high-k dielectric layer separates the source electrode from the gate electrode and substrate and separates the drain electrode from the gate electrode and the substrate. First and second oxide layers are formed over the gate dielectric and are located adjacent to the source electrode on the first side of the gate electrode and located adjacent to the drain electrode on the second side of the gate electrode. A semiconductor layer is formed over the first oxide layer, the second oxide layer, the source electrode, the drain electrode, and the gate dielectric.
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10.
公开(公告)号:US20210375991A1
公开(公告)日:2021-12-02
申请号:US17222123
申请日:2021-04-05
发明人: Yen-Chung HO , Yong-Jie WU , Chia-Jung YU , Hui-Hsien WEI , Mauricio MANFRINI , Ken-Ichi GOTO , Pin-Cheng HSU
IPC分类号: H01L27/24 , H01L27/11507 , H01L27/22
摘要: A memory device and method of making the same, the memory device including a substrate, a thin film transistor (TFT) disposed on the substrate; and a memory cell disposed on the substrate and overlapped with the TFT. The TFT is configured to selectively supply power to the memory cell memory cell.
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