公开(公告)号：US12127489B2

公开(公告)日：2024-10-22

申请号：US18170947

申请日：2023-02-17

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Tai-Yen Peng ,  Hui-Hsien Wei ,  Wei-Chih Wen ,  Pin-Ren Dai ,  Chien-Min Lee ,  Han-Ting Tsai ,  Jyu-Horng Shieh ,  Chung-Te Lin

IPC: H10B63/00 ,  H10B61/00 ,  H10N50/01 ,  H10N50/80 ,  H10N70/00 ,  H10N70/20

CPC classification number: H10N70/884 ,  H10B61/22 ,  H10B63/30 ,  H10B63/82 ,  H10B63/84 ,  H10N50/01 ,  H10N50/80 ,  H10N70/023 ,  H10N70/063 ,  H10N70/24 ,  H10N70/245 ,  H10N70/826 ,  H10N70/8416 ,  H10N70/8833

Abstract: An IC structure comprises a substrate, a first dielectric structure, a second dielectric structure, a first via structure, and a memory cell structure. The substrate comprises a memory region and a logic region. The first dielectric structure is over the memory region. The second dielectric structure laterally extends from the first dielectric structure to over the logic region. The second dielectric structure has a thickness less than a thickness of the first dielectric structure. The first via structure extends through the first dielectric structure. A top segment of the first via structure is higher than a top surface of the first dielectric structure. The first memory cell structure is over the first via structure.

公开(公告)号：US12127485B2

公开(公告)日：2024-10-22

申请号：US17421418

申请日：2020-01-07

Applicant: NANOBRIDGE SEMICONDUCTOR, INC.

Inventor： Naoki Banno ,  Munehiro Tada ,  Hideaki Numata ,  Koichiro Okamoto

IPC: H01L27/24 ,  H10B63/00 ,  H10N70/00

CPC classification number: H10N70/023 ,  H10B63/30 ,  H10N70/063 ,  H10N70/8416 ,  H10N70/883

Abstract: A switching element that has reduced switching voltage and leakage current and that demonstrates high reliability and low power consumption is achieved as a result of comprising: a first insulation layer in which first wiring mainly consisting of copper is embedded in a first wiring groove that opens upward; a second insulation layer which is formed on an upper surface of the first insulation layer and the first wiring and has an opening that reaches the first insulation layer and the first wiring; a first electrode which is the portion of the first wiring that is exposed from the opening; an oxygen supply layer which is formed on an upper surface of the second insulation layer, generates oxygen plasma during etching to form the opening in the second insulation layer, and remains at least in the vicinity of the opening of the upper surface of the second insulation layer; an ion conducting layer which is formed on the upper surface of the first insulation layer and the first electrode that are exposed from the opening, an inner surface of the opening of the second insulation layer, and an upper surface of the oxygen supply layer; and a second electrode that is formed on an upper surface of the ion conducting layer.

公开(公告)号：US12119055B2

公开(公告)日：2024-10-15

申请号：US17329028

申请日：2021-05-24

Applicant: Micron Technology, Inc.

Inventor： Hernan A. Castro ,  Everardo Torres Flores ,  Jeremy M. Hirst

IPC: G11C13/00 ,  G11C5/02 ,  G11C5/06 ,  H10B63/00 ,  G11C8/08 ,  H10N70/00 ,  H10N70/20

CPC classification number: G11C13/0004 ,  G11C5/025 ,  G11C5/063 ,  G11C13/0023 ,  H10B63/24 ,  H10B63/30 ,  H10B63/80 ,  H10B63/84 ,  G11C8/08 ,  G11C2213/71 ,  G11C2213/77 ,  H10N70/231 ,  H10N70/826 ,  H10N70/8828

Abstract: Row electrode drivers and column electrode drivers for a memory device are distributed within a footprint share by a memory cell array.

公开(公告)号：US12075713B2

公开(公告)日：2024-08-27

申请号：US18321843

申请日：2023-05-23

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Jau-Yi Wu

IPC: H10N70/00 ,  H10B63/00 ,  H10N70/20

CPC classification number: H10N70/826 ,  H10B63/30 ,  H10N70/021 ,  H10N70/231 ,  H10N70/841

Abstract: A device and a method of forming the same are provided. The device includes a substrate, a first dielectric layer over the substrate, a bottom electrode extending through the first dielectric layer, a first buffer layer over the bottom electrode, a phase-change layer over the first buffer layer, a top electrode over the phase-change layer, and a second dielectric layer over the first dielectric layer. The second dielectric layer surrounds the phase-change layer and the top electrode. A width of the top electrode is greater than a width of the bottom electrode.

公开(公告)号：US12058943B2

公开(公告)日：2024-08-06

申请号：US18105935

申请日：2023-02-06

Applicant: International Business Machines Corporation

Inventor： Nanbo Gong ,  Guy M. Cohen ,  Takashi Ando

IPC: H10N70/20 ,  G11C13/00 ,  H10B63/00 ,  H10N70/00

CPC classification number: H10N70/231 ,  G11C13/0004 ,  G11C13/0069 ,  H10B63/30 ,  H10N70/8413 ,  G11C2013/008

Abstract: An apparatus comprises a phase-change material, a first electrode at a first end of the phase-change material, a second electrode at a second end of the phase-change material, and a heating element coupled to a least a given portion of the phase-change material between the first end and the second end. The apparatus also comprises a first input terminal coupled to the heating element, a second input terminal coupled to the heating element, and an output terminal coupled to the second electrode.

公开(公告)号：US20240237359A1

公开(公告)日：2024-07-11

申请号：US18152072

申请日：2023-01-09

Applicant: TetraMem Inc.

Inventor： Ning Ge ,  Minxian Zhang ,  Mingche Wu ,  Gary Miner

IPC: H10B63/00 ,  H10N70/00 ,  H10N70/20

CPC classification number: H10B63/84 ,  H10B63/30 ,  H10N70/063 ,  H10N70/253 ,  H10N70/841 ,  H10N70/8833

Abstract: An apparatus including a plurality of resistive random-access memory (RRAM) devices is provided. The RRAM devices are fabricated on a single substrate in some embodiments. The apparatus includes an interconnect layer fabricated on the substrate. A first RRAM device of the RRAM devices includes a first bottom electrode, a first top electrode; and a first filament-forming layer fabricated between the first bottom electrode and the first top electrode. A second RRAM device of the RRAM devices includes a second bottom electrode, a second top electrode, and a second filament-forming layer fabricated between the second bottom electrode and the second top electrode. The first bottom electrode and the second bottom electrode are fabricated on multiple metallic pads or metallic vias of the interconnect layer. The first filament-forming layer and the second filament-forming layer include different switching oxides.

公开(公告)号：US20240234579A1

公开(公告)日：2024-07-11

申请号：US18444520

申请日：2024-02-16

Applicant: Intel Corporation

Inventor： Abhishek A. Sharma ,  Arnab Sen Gupta ,  Travis W. LaJoie ,  Sarah Atanasov ,  Chieh-Jen Ku ,  Bernhard Sell ,  Noriyuki Sato ,  Van Le ,  Matthew Metz ,  Hui Jae Yoo ,  Pei-Hua Wang

IPC: H01L29/786 ,  H01L29/66 ,  H10B61/00 ,  H10B63/00

CPC classification number: H01L29/7869 ,  H01L29/66969 ,  H10B61/22 ,  H10B63/30

Abstract: A thin film transistor (TFT) structure includes a gate electrode, a gate dielectric layer on the gate electrode, a channel layer including a semiconductor material with a first polarity on the gate dielectric layer. The TFT structure also includes a multi-layer material stack on the channel layer, opposite the gate dielectric layer, an interlayer dielectric (ILD) material over the multi-layer material stack and beyond a sidewall of the channel layer. The TFT structure further includes source and drain contacts through the interlayer dielectric material, and in contact with the channel layer, where the multi-layer material stack includes a barrier layer including oxygen and a metal in contact with the channel layer, where the barrier layer has a second polarity. A sealant layer is in contact with the barrier layer, where the sealant layer and the ILD have a different composition.

公开(公告)号：US20240203472A1

公开(公告)日：2024-06-20

申请号：US18589540

申请日：2024-02-28

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Fa-Shen Jiang ,  Hsia-Wei Chen ,  Hsun-Chung Kuang ,  Hai-Dang Trinh ,  Cheng-Yuan Tsai

IPC: G11C11/16 ,  G11C11/56 ,  H10B53/30 ,  H10B61/00 ,  H10B63/00

CPC classification number: G11C11/161 ,  G11C11/1657 ,  G11C11/1659 ,  G11C11/5614 ,  G11C11/5657 ,  G11C11/5678 ,  H10B53/30 ,  H10B61/22 ,  H10B63/30

Abstract: Various embodiments of the present disclosure are directed towards a memory device. The memory device has a first transistor having a first source/drain and a second source/drain, where the first source/drain and the second source/drain are disposed in a semiconductor substrate. A dielectric structure is disposed over the semiconductor substrate. A first memory cell is disposed in the dielectric structure and over the semiconductor substrate, where the first memory cell has a first electrode and a second electrode, where the first electrode of the first memory cell is electrically coupled to the first source/drain of the first transistor. A second memory cell is disposed in the dielectric structure and over the semiconductor substrate, where the second memory cell has a first electrode and a second electrode, where the first electrode of the second memory cell is electrically coupled to the second source/drain of the first transistor.

公开(公告)号：US12004435B2

公开(公告)日：2024-06-04

申请号：US17804912

申请日：2022-06-01

Applicant: International Business Machines Corporation

Inventor： Min Gyu Sung ,  Soon-Cheon Seo ,  Chanro Park

IPC: G11C11/00 ,  H10B63/00 ,  H10N70/00

CPC classification number: H10N70/8418 ,  H10B63/30 ,  H10N70/063 ,  H10N70/828 ,  H10N70/8833

Abstract: A method of manufacturing an RRAM cell includes forming a first wire, forming an insulator on the first wire, the insulator having a pore and an insulator surface, and forming a first electrode layer on the first wire and the insulator, the first electrode having an electrode surface. The method further includes recessing the first electrode layer such that the electrode surface is recessed toward the first wire from the insulator surface, forming a switching layer on the insulator and the first electrode, and forming a second electrode on the switching layer.

公开(公告)号：US11985909B2

公开(公告)日：2024-05-14

申请号：US16435875

申请日：2019-06-10

Applicant: Intel Corporation

Inventor： Elijah Karpov ,  Mauro Kobrinsky

IPC: G11C11/00 ,  G11C13/00 ,  H10B63/00 ,  H10N70/00 ,  H10N70/20

CPC classification number: H10N70/231 ,  G11C13/0004 ,  G11C13/0069 ,  G11C13/0097 ,  H10B63/20 ,  H10B63/24 ,  H10B63/30 ,  H10N70/826 ,  H10N70/841 ,  H10N70/8828 ,  G11C13/004 ,  G11C2013/0092 ,  G11C2213/52 ,  G11C2213/72 ,  G11C2213/79

Abstract: Embodiments disclosed herein include memory bitcells and methods of forming such memory bitcells. In an embodiment, the memory bitcell is part of an embedded DRAM (eDRAM) memory device. In an embodiment, the memory bitcell comprises a substrate and a storage element embedded in the substrate. In an embodiment, the storage element comprises a phase changing material that comprises a binary alloy. In an embodiment, the memory bitcell further comprises a first electrode over a first surface of the storage element, and a second electrode over a second surface of the storage element.