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公开(公告)号：US09990995B2
公开(公告)日：2018-06-05
申请号：US15854934
申请日：2017-12-27
Applicant: MICRON TECHNOLOGY, INC.
Inventor： Andrea Redaelli
CPC classification number: G11C13/0069 , G11C7/04 , G11C11/5685 , G11C13/0002 , G11C13/0004 , G11C13/0028 , G11C13/0033 , G11C13/004 , G11C2013/008 , G11C2013/0088 , H01L27/2445 , H01L27/2472 , H01L45/06 , H01L45/1233 , H01L45/126 , H01L45/141 , H01L45/144
Abstract: Systems having a resistive memory device having control circuitry configured to build a data word from remapped data bits from a received data word such that pairs of data bits are mapped to adjacent locations in the built data word, the control circuitry further configured to program the built data word to memory cells coupled to a selected data line such that, during a same program operation, pairs of adjacent memory cells along the selected data line are programmed with the pairs of data.
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公开(公告)号：US20180122474A1
公开(公告)日：2018-05-03
申请号：US15854934
申请日：2017-12-27
Applicant: MICRON TECHNOLOGY, INC.
Inventor： Andrea Redaelli
CPC classification number: G11C13/0069 , G11C7/04 , G11C11/5685 , G11C13/0002 , G11C13/0004 , G11C13/0028 , G11C13/0033 , G11C13/004 , G11C2013/008 , G11C2013/0088 , H01L27/2445 , H01L27/2472 , H01L45/06 , H01L45/1233 , H01L45/126 , H01L45/141 , H01L45/144
Abstract: Systems having a resistive memory device having control circuitry configured to build a data word from remapped data bits from a received data word such that pairs of data bits are mapped to adjacent locations in the built data word, the control circuitry further configured to program the built data word to memory cells coupled to a selected data line such that, during a same program operation, pairs of adjacent memory cells along the selected data line are programmed with the pairs of data.
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公开(公告)号：US09892785B2
公开(公告)日：2018-02-13
申请号：US15442594
申请日：2017-02-24
Applicant: Intel Corporation
Inventor： Sanjay Rangan , Kiran Pangal , Nevil N Gajera , Lu Liu , Gayathri Rao Subbu
CPC classification number: G11C13/0069 , G11C7/04 , G11C11/16 , G11C13/0004 , G11C13/0061 , G11C2013/0078 , G11C2013/008 , G11C2013/0092 , H01L45/06 , H01L45/1286 , H01L45/141
Abstract: Phase change material can be set with a multistage set process. Set control logic can heat a phase change semiconductor material (PM) to a first temperature for a first period of time. The first temperature is configured to promote nucleation of a crystalline state of the PM. The control logic can increase the temperature to a second temperature for a second period of time. The second temperature is configured to promote crystal growth within the PM. The nucleation and growth of the crystal set the PM to the crystalline state. The multistage ramping up of the temperature can improve the efficiency of the set process relative to traditional approaches.
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公开(公告)号：US09881673B2
公开(公告)日：2018-01-30
申请号：US15488828
申请日：2017-04-17
Applicant: MICRON TECHNOLOGY, INC.
Inventor： Andrea Redaelli
CPC classification number: G11C13/0069 , G11C7/04 , G11C11/5685 , G11C13/0002 , G11C13/0004 , G11C13/0028 , G11C13/0033 , G11C13/004 , G11C2013/008 , G11C2013/0088 , H01L27/2445 , H01L27/2472 , H01L45/06 , H01L45/1233 , H01L45/126 , H01L45/141 , H01L45/144
Abstract: Memories having a plurality of resistive storage elements in a shared resistance variable material, a plurality of select devices coupled to the plurality of resistive storage elements in a one-to-one relationship and sense circuitry coupled to the plurality of select devices.
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公开(公告)号：US09870822B2
公开(公告)日：2018-01-16
申请号：US15102718
申请日：2013-12-18
Applicant: HEWLETT-PACKARD DEVELOPMENT COMPANY, L.P.
Inventor： Ning Ge , Jianhua Yang , Zhiyong Li
CPC classification number: G11C13/0069 , G11C7/04 , G11C11/56 , G11C11/5678 , G11C11/5685 , G11C13/0002 , G11C13/0004 , G11C13/0007 , G11C2013/008 , G11C2213/32 , H01L27/2463 , H01L45/08 , H01L45/1233 , H01L45/1286 , H01L45/145 , H01L45/146 , H01L45/16
Abstract: A non-volatile memory element with thermal-assisted switching control is disclosed. The non-volatile memory element is disposed on a thermal inkjet resistor. Methods for manufacturing the combination and methods of using the combination are also disclosed.
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Patent Agency Ranking
公开(公告)号：US20170186948A1
公开(公告)日：2017-06-29
申请号：US15163596
申请日：2016-05-24
Applicant: SK hynix Inc.
Inventor： Kyung-Wan KIM
CPC classification number: G11C13/004 , G11C13/0007 , G11C13/0069 , G11C13/0097 , G11C2013/008 , G11C2013/0083 , H01L45/08 , H01L45/1233 , H01L45/146 , H01L45/1641
Abstract: A method for fabricating a semiconductor device and a method for operating the semiconductor device are provided. The method for fabricating a semiconductor device includes forming a first electrode layer; forming a material layer, including conductive path components, over the first electrode layer; forming a second electrode layer over the material layer; performing a forming operation, which includes initially creating, in the material layer, a conductive path that electrically connects the first electrode layer to the second electrode layer by applying one of a predetermined voltage and a predetermined current between the first and second electrode layers, the conductive path including the conductive path components; and performing a first heat-treatment process at a predetermined temperature that removes some of the conductive path components from the conductive path, wherein a resistance state of the material layer changes based on the creation or dissolution of the conductive paths.
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公开(公告)号：US09583187B2
公开(公告)日：2017-02-28
申请号：US14672130
申请日：2015-03-28
Applicant: Intel Corporation
Inventor： Sanjay Rangan , Kiran Pangal , Nevil N Gajera , Lu Liu , Gayathri Rao Subbu
CPC classification number: G11C13/0069 , G11C7/04 , G11C11/16 , G11C13/0004 , G11C13/0061 , G11C2013/0078 , G11C2013/008 , G11C2013/0092 , H01L45/06 , H01L45/1286 , H01L45/141
Abstract: Phase change material can be set with a multistage set process. Set control logic can heat a phase change semiconductor material (PM) to a first temperature for a first period of time. The first temperature is configured to promote nucleation of a crystalline state of the PM. The control logic can increase the temperature to a second temperature for a second period of time. The second temperature is configured to promote crystal growth within the PM. The nucleation and growth of the crystal set the PM to the crystalline state. The multistage ramping up of the temperature can improve the efficiency of the set process relative to traditional approaches.
Abstract translation: 相变材料可以通过多级设定过程进行设置。 设置控制逻辑可以将相变半导体材料（PM）加热到第一温度一段时间。 第一温度被配置成促进PM的结晶状态的成核。 控制逻辑可以将温度升高到第二温度持续第二时间段。 第二温度被配置为促进PM内的晶体生长。 晶体的成核和生长将PM设置为结晶状态。 相对于传统方法，多级升温可以提高设定过程的效率。
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公开(公告)号：US20170032837A1
公开(公告)日：2017-02-02
申请号：US15102718
申请日：2013-12-18
Applicant: HEWLETT-PACKARD DEVELOPMENT COMPANY, L.P.
Inventor： Ning Ge , Jianhua Yang , Zhiyong Li
CPC classification number: G11C13/0069 , G11C7/04 , G11C11/56 , G11C11/5678 , G11C11/5685 , G11C13/0002 , G11C13/0004 , G11C13/0007 , G11C2013/008 , G11C2213/32 , H01L27/2463 , H01L45/08 , H01L45/1233 , H01L45/1286 , H01L45/145 , H01L45/146 , H01L45/16
Abstract: A non-volatile memory element with thermal-assisted switching control is disclosed. The non-volatile memory element is disposed on a thermal inkjet resistor. Methods for manufacturing the combination and methods of using the combination are also disclosed.
Abstract translation: 公开了一种具有热辅助切换控制的非易失性存储元件。 非易失性存储元件设置在热喷墨电阻器上。 还公开了制造组合的方法和使用该组合的方法。
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9.发明申请公开(公告)号：US20160380194A1
公开(公告)日：2016-12-29
申请号：US14752935
申请日：2015-06-27
Applicant: Intel Corporation
Inventor： Elijah V. Karpov , Prashant Majhi , Niloy Mukherjee , Ravi Pillarisetty , Uday Shah , Brian S. Doyle , Robert S. Chau
CPC classification number: H01L45/1293 , G11C13/0002 , G11C13/0004 , G11C13/0007 , G11C13/0009 , G11C13/0069 , G11C2013/008 , H01L27/2409 , H01L27/2418 , H01L27/2463 , H01L45/08 , H01L45/085 , H01L45/1233 , H01L45/1253 , H01L45/128 , H01L45/141 , H01L45/144 , H01L45/146
Abstract: Heat-trapping bulk layers or thermal-boundary film stacks are formed between a heat-assisted active layer and an associated electrode to confine such transient heat to the active layer in a heat-assisted device (e.g., certain types of resistance-switching and selector elements used in non-volatile memory. Preferably, the heat-trapping layers or thermal-boundary stacks are electrically conductive while being thermally insulating or reflective. Heat-trapping layers use bulk absorption and re-radiation to trap heat. Materials may include, without limitation, chalcogenides with Group 6 elements. Thermal-boundary stacks use reflection from interfaces to trap heat and may include film layers as thin as 1-5 monolayers. Effectiveness of a thermal-boundary stack depends on the thermal impedance mismatch between layers of the stack, rendering thermally insulating bulk materials optional for thermal-boundary stack components.
Abstract translation: 在热辅助有源层和相关电极之间形成热捕获本体层或热边界膜堆，以将这种瞬态热量限制在热辅助装置中的有源层（例如，某些类型的电阻切换和选择器 在非易失性存储器中使用的元件优选地，热捕获层或热边界堆叠是导热的，同时是绝热或反射的。热捕获层使用大量吸收和再辐射来捕获热量，材料可以包括，没有 热边界堆叠使用界面的反射来捕获热量，并且可能包括薄至1-5单层的薄膜层。热边界堆叠的有效性取决于堆叠层之间的热阻抗失配 ，为热边界堆叠组件提供可选的绝热散装材料。
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公开(公告)号：US20160365142A1
公开(公告)日：2016-12-15
申请号：US15245249
申请日：2016-08-24
Applicant: Micron Technology, Inc.
Inventor： Ugo Russo , Andrea Redaelli , Fabio Pellizzer
IPC: G11C13/00
CPC classification number: G11C13/0004 , G11C11/5678 , G11C13/003 , G11C13/004 , G11C13/0069 , G11C2013/008 , H01L45/06 , H01L45/08 , H01L45/1233 , H01L45/14 , H01L45/145 , H01L45/16
Abstract: Resistance variable memory cells having a plurality of resistance variable materials and methods of operating and forming the same are described herein. As an example, a resistance variable memory cell can include a plurality of resistance variable materials located between a plug material and an electrode material. The resistance variable memory cell also includes a first conductive material that contacts the plug material and each of the plurality of resistance variable materials and a second conductive material that contacts the electrode material and each of the plurality of resistance variable materials.
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