公开(公告)号：US20230360701A1

公开(公告)日：2023-11-09

申请号：US18353454

申请日：2023-07-17

Applicant: Cyberswarm, INC

Inventor： Viorel-Georgel DUMITRU ,  Cristina Besleaga stan ,  Alin Velea ,  Aurelian-Catalin Galca

IPC: G11C13/00 ,  G11C11/56

CPC classification number: G11C13/0069 ,  G11C11/5685 ,  G11C13/0007 ,  G11C13/0038 ,  G11C13/004

Abstract: A programmable resistive memory element and a method of adjusting a resistance of a programmable resistive memory element are provided. The programmable resistive memory element includes at least one resistive memory element. Each resistive memory element includes an Indium-Gallium-Zinc-Oxide (IGZO) resistive layer, a first electrical contact and a second electrical contact. The first and second electrical contacts are disposed on the IGZO resistive layer in the same plane. The programmable resistive memory element includes a voltage generator coupled to the first and second electrical contacts, constructed and arranged to apply a thermal treatment to the resistive memory element to adjust a resistance of the resistive memory element.

公开(公告)号：US11672189B2

公开(公告)日：2023-06-06

申请号：US17194609

申请日：2021-03-08

Applicant: HEFEI RELIANCE MEMORY LIMITED

Inventor： Darrell Rinerson ,  Christophe J. Chevallier ,  Wayne Kinney ,  Roy Lambertson ,  John E. Sanchez, Jr. ,  Lawrence Schloss ,  Philip Swab ,  Edmond Ward

IPC: H10N70/20 ,  G11C11/56 ,  G11C13/00 ,  H10N70/00 ,  H10B63/00 ,  G06F30/30 ,  H01L45/00 ,  H01L27/24

CPC classification number: H01L45/08 ,  G06F30/30 ,  G11C11/5685 ,  G11C13/004 ,  G11C13/0007 ,  G11C13/0009 ,  G11C13/0069 ,  H01L27/2436 ,  H01L27/2481 ,  H01L45/085 ,  H01L45/1233 ,  H01L45/1246 ,  H01L45/1253 ,  H01L45/146 ,  H01L45/147 ,  H01L45/1625 ,  G11C2013/005 ,  G11C2013/009 ,  G11C2013/0045 ,  G11C2213/11 ,  G11C2213/31 ,  G11C2213/32 ,  G11C2213/53 ,  G11C2213/54 ,  G11C2213/56 ,  G11C2213/71 ,  G11C2213/79

Abstract: A memory using mixed valence conductive oxides is disclosed. The memory includes a mixed valence conductive oxide that is less conductive in its oxygen deficient state and a mixed electronic ionic conductor that is an electrolyte to oxygen and promotes an electric filed to cause oxygen ionic motion.

公开(公告)号：US20190065117A1

公开(公告)日：2019-02-28

申请号：US16073143

申请日：2016-03-31

Applicant: Hewlett Packard Enterprise Development LP

Inventor： Naveen Muralimanohar ,  Ali Shafiee Ardestani

IPC: G06F3/06 ,  G06F17/30 ,  G11C13/00

CPC classification number: G06F3/0659 ,  G06F3/0604 ,  G06F3/0683 ,  G06F16/2237 ,  G06F16/2379 ,  G06J1/00 ,  G06T1/60 ,  G11C11/56 ,  G11C11/5685 ,  G11C13/0002

Abstract: In an example, a method comprises receiving a first matrix of values to be mapped to a resistive memory array, wherein each value in the matrix is to be represented as a resistance of a resistive memory element. An outlying value may be identified in the first matrix. At least one value of a portion of the first matrix containing the outlying value may be substituted with at least one substitute value to form a substituted first matrix.

公开(公告)号：US20180330790A1

公开(公告)日：2018-11-15

申请号：US16017249

申请日：2018-06-25

Applicant: Zeno Semiconductor, Inc.

Inventor： Yuniarto Widjaja

IPC: G11C14/00 ,  H01L27/102 ,  H01L45/00 ,  H01L27/12 ,  G11C13/00 ,  G11C11/402 ,  G11C11/4067

CPC classification number: G11C14/0045 ,  G06F3/0619 ,  G06F3/0647 ,  G06F3/0685 ,  G11C11/14 ,  G11C11/4026 ,  G11C11/404 ,  G11C11/4067 ,  G11C11/5678 ,  G11C11/5685 ,  G11C13/0004 ,  G11C13/0007 ,  G11C13/0033 ,  G11C13/004 ,  G11C13/0069 ,  G11C2013/0045 ,  G11C2013/0078 ,  G11C2211/4016 ,  G11C2211/5643 ,  G11C2213/31 ,  G11C2213/32 ,  H01L27/1023 ,  H01L27/108 ,  H01L27/10802 ,  H01L27/10897 ,  H01L27/1203 ,  H01L27/24 ,  H01L27/2445 ,  H01L27/2463 ,  H01L29/7841 ,  H01L45/06 ,  H01L45/065 ,  H01L45/08 ,  H01L45/085 ,  H01L45/1233 ,  H01L45/1253 ,  H01L45/141 ,  H01L45/144 ,  H01L45/146 ,  H01L45/147

Abstract: Semiconductor memory is provided wherein a memory cell includes a capacitorless transistor having a floating body configured to store data as charge therein when power is applied to the cell. The cell further includes a nonvolatile memory comprising a resistance change element configured to store data stored in the floating body under any one of a plurality of predetermined conditions. A method of operating semiconductor memory to function as volatile memory, while having the ability to retain stored data when power is discontinued to the semiconductor memory is described.

公开(公告)号：US20180082742A1

公开(公告)日：2018-03-22

申请号：US15460600

申请日：2017-03-16

Applicant: TOSHIBA MEMORY CORPORATION

Inventor： Yusuke ARAYASHIKI

IPC: G11C13/00 ,  H01L45/00 ,  H01L27/24

CPC classification number: G11C13/0069 ,  G11C11/5614 ,  G11C11/5678 ,  G11C11/5685 ,  G11C13/0004 ,  G11C13/0007 ,  G11C13/0011 ,  G11C13/003 ,  G11C13/004 ,  G11C13/0064 ,  G11C2013/0066 ,  G11C2013/0073 ,  G11C2013/0092 ,  G11C2213/71 ,  H01L27/2454 ,  H01L27/249 ,  H01L45/085 ,  H01L45/1233 ,  H01L45/1253 ,  H01L45/145

Abstract: A memory device includes a first interconnect extending in a first direction, a second interconnect extending in a second direction crossing the first direction, a third interconnect extending in a third direction crossing a plane including the first direction and the second direction, a fourth interconnect extending in the third direction, a semiconductor member, a first resistance change film, and a second resistance change film. The semiconductor member is connected between a first end of the second interconnect and the first interconnect. The first resistance change film is connected between a side surface of the second interconnect and the third interconnect. The second resistance change film is connected between a second end of the second interconnect and the fourth interconnect.

公开(公告)号：US09887004B2

公开(公告)日：2018-02-06

申请号：US15194678

申请日：2016-06-28

Applicant: HGST Netherlands B.V.

Inventor： James Edwin O'Toole ,  Ward Parkinson ,  Daniel Robert Shepard ,  Thomas Michael Trent

IPC: G11C13/00 ,  H01L45/00 ,  H01L27/24 ,  G11C11/00

CPC classification number: G11C13/0069 ,  G11C11/00 ,  G11C11/5678 ,  G11C11/5685 ,  G11C13/0004 ,  G11C13/0007 ,  G11C13/0023 ,  G11C13/003 ,  G11C13/004 ,  G11C2013/0073 ,  G11C2213/76 ,  H01L27/2427 ,  H01L27/2463 ,  H01L45/085 ,  H01L45/1233 ,  H01L45/146

Abstract: The present disclosure generally relates to the fabrication of and methods for creating a reversible tri-state memory device which provides both forward and reverse write and read drive to a bi-directional RRAM cell, thus allowing writing in the forward and reverse directions. The memory device, however, utilizes a single transistor “on pitch” which fits between two metal lines traversing the array tile.

公开(公告)号：US20170373248A1

公开(公告)日：2017-12-28

申请号：US15683636

申请日：2017-08-22

Applicant: Intel Corporation

Inventor： Valter Soncini ,  Davide Erbetta

IPC: H01L45/00

CPC classification number: H01L45/14 ,  G11C11/5678 ,  G11C11/5685 ,  H01L27/2427 ,  H01L27/2463 ,  H01L45/00 ,  H01L45/04 ,  H01L45/06 ,  H01L45/122 ,  H01L45/1233 ,  H01L45/1253 ,  H01L45/143 ,  H01L45/144 ,  H01L45/148 ,  H01L45/16 ,  H01L45/1625

Abstract: Phase change memory cells, structures, and devices having a phase change material and an electrode forming an ohmic contact therewith are disclosed and described. Such electrodes can have a resistivity of from 10 to 100 mOhm·cm.

公开(公告)号：US09842646B2

公开(公告)日：2017-12-12

申请号：US15500555

申请日：2015-04-28

Applicant: Hewlett Packard Enterprise Development LP

Inventor： Miao Hu ,  Ning Ge ,  John Paul Strachan ,  R. Stanley Williams

IPC: G11C11/00 ,  G11C13/00

CPC classification number: G11C13/004 ,  G06N3/049 ,  G06N3/0635 ,  G11C11/54 ,  G11C11/5685 ,  G11C13/0004 ,  G11C13/0007 ,  G11C13/003 ,  G11C13/0038 ,  G11C13/0061 ,  G11C13/0069 ,  G11C27/005 ,  G11C2213/74 ,  G11C2213/75 ,  G11C2213/76 ,  G11C2213/79

Abstract: In an example, a memristor apparatus with variable transmission delay may include a first memristor programmable to have one of a plurality of distinct resistance levels, a second memristor, a transistor connected between the first memristor and the second memristor, and a capacitor having a capacitance, in which the capacitor is connected between the first memristor and the transistor. In addition, application of a reading voltage across the second memristor is delayed by a time period equivalent to the programmed resistance level of the first memristor and the capacitance of the capacitor.

公开(公告)号：US09831287B2

公开(公告)日：2017-11-28

申请号：US15277551

申请日：2016-09-27

Applicant: Micron Technology, Inc.

Inventor： Chandra Mouli

IPC: G11C5/02 ,  H01L27/24 ,  G11C11/56 ,  G11C13/00 ,  H01L45/00 ,  G11C11/34 ,  H01L29/66

CPC classification number: H01L27/2418 ,  G11C5/02 ,  G11C11/34 ,  G11C11/39 ,  G11C11/4026 ,  G11C11/5664 ,  G11C11/5678 ,  G11C11/5685 ,  G11C13/0002 ,  G11C13/0004 ,  G11C13/0007 ,  G11C13/0014 ,  G11C13/0016 ,  G11C13/003 ,  G11C2013/009 ,  G11C2213/72 ,  G11C2213/74 ,  G11C2213/76 ,  G11C2216/08 ,  H01L29/6609 ,  H01L45/00 ,  H01L45/141 ,  H01L45/145 ,  H01L45/16

Abstract: Some embodiments include memory devices having a wordline, a bitline, a memory element selectively configurable in one of three or more different resistive states, and a diode configured to allow a current to flow from the wordline through the memory element to the bitline responsive to a voltage being applied across the wordline and the bitline and to decrease the current if the voltage is increased or decreased. Some embodiments include memory devices having a wordline, a bitline, memory element selectively configurable in one of two or more different resistive states, a first diode configured to inhibit a first current from flowing from the bitline to the wordline responsive to a first voltage, and a second diode comprising a dielectric material and configured to allow a second current to flow from the wordline to the bitline responsive to a second voltage.

公开(公告)号：US20170329724A1

公开(公告)日：2017-11-16

申请号：US15527374

申请日：2015-10-08

Applicant: SONY CORPORATION

Inventor： HARUHIKO TERADA ,  LUI SAKAI ,  HIDEAKI OKUBO ,  KEIICHI TSUTSUI

IPC: G06F12/16 ,  G06F11/22 ,  G06F11/14

CPC classification number: G06F12/16 ,  G06F11/1441 ,  G06F11/22 ,  G11C11/5685 ,  G11C13/0023 ,  G11C13/0033 ,  G11C13/004 ,  G11C29/028 ,  G11C2013/0054

Abstract: To suppress the degradation of memory cells in a non-volatile memory. A read processing unit performs a read process for reading read data from each of a plurality of memory cells on the basis of a first threshold. An error detection unit detects presence or absence of an error in the read data and specifies memory cells in which the error is present among the plurality of memory cells. A re-read processing unit performs a re-read process for reading data, as re-read data, from the specified memory cells on the basis of a second threshold different from the first threshold. A refresh processing unit rewrites, for a memory cell of which the re-read data has a different value from the read data among the specified memory cells, data with the re-read data as a refresh process.