公开(公告)号：US20240355386A1

公开(公告)日：2024-10-24

申请号：US18302278

申请日：2023-04-18

Applicant: TetraMem Inc.

Inventor： Hengfang Zhu ,  Wenbo Yin ,  Miao Hu

IPC: G11C13/00

CPC classification number: G11C13/003 ,  G11C13/004 ,  G11C2213/79

Abstract: The present disclosure relates to voltage-mode crossbar circuits that may include a plurality of bit lines intersecting with a plurality of word lines, a plurality of cross-point devices, and a plurality of sensing circuits configured to amplify bit line voltages settled on the bit lines in response to an application of input voltages to the cross-point devices via the word lines and generate digital outputs representative of the amplified bit line voltages. Each cross-point device is connected to one of the word lines and one of the bit lines and may include a resistive random-access memory (RRAM) device. Each cross-point device may further be connected to a local select line that may enable a group of cross-point devices connected to one or more bit lines. A cross-point device may be enabled when both a global select line and the local select line connected to the cross-point device are enabled.

公开(公告)号：US12050997B2

公开(公告)日：2024-07-30

申请号：US16884130

申请日：2020-05-27

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Hsinyu Tsai ,  Geoffrey Burr ,  Pritish Narayanan ,  Malte Johannes Rasch

IPC: G06N3/084 ,  G11C7/10 ,  G11C11/54 ,  G11C13/00 ,  G06N3/063

CPC classification number: G06N3/084 ,  G11C7/1006 ,  G11C11/54 ,  G11C13/0069 ,  G06N3/063 ,  G11C2213/77 ,  G11C2213/79

Abstract: A computer implemented method for implementing a convolutional neural network (CNN) using a crosspoint array includes configuring the crosspoint array to implement a convolution layer by storing one or more weights in crosspoint devices of the array. The method further includes making multiple copies of the weights and training the CNN. Training the CNN includes mapping input data of the convolution layer to the crosspoint array in a row-by-row manner. Further the excitation is input in a row-by-row manner into the crosspoint array, thereby creating row-by-row forward output from the crosspoint array. Further, outputs from the crosspoint devices are stored to corresponding integrators. Errors in the outputs as compared to a desired output, from multiple rows are computed and back propagated in a row-by-row manner into the crosspoint array, the computed errors transmitted to a previous convolution layer.

公开(公告)号：US12016169B2

公开(公告)日：2024-06-18

申请号：US17842208

申请日：2022-06-16

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Ping-Wei Wang ,  Lien Jung Hung ,  Kuo-Hsiu Hsu ,  Kian-Long Lim ,  Yu-Kuan Lin ,  Chia-Hao Pao ,  Chih-Chuan Yang ,  Shih-Hao Lin ,  Choh Fei Yeap

IPC: H01L23/528 ,  G11C11/412 ,  G11C11/419 ,  H01L21/66 ,  H04N21/426 ,  H10B10/00 ,  H10B41/35

CPC classification number: H10B10/12 ,  G11C11/412 ,  G11C11/419 ,  H01L22/12 ,  H01L23/528 ,  H04N21/42692 ,  H10B10/00 ,  H10B41/35 ,  G11C2213/74 ,  G11C2213/79 ,  H01L2924/1437

Abstract: A memory device includes a memory array having a plurality of memory cells. Each memory cell of the plurality of memory cells includes a substrate having a front side and a back side with a transistor of the memory cell being formed on the front side and the back side being opposite of the front side, a first interconnect layer on the front side to provide a bit line of the memory cell, a second interconnect layer on the front side to provide a word line of the memory cell, a third interconnect layer on the back side to provide a supply voltage to the memory cell and a fourth interconnect layer on the back side to provide a ground voltage to the memory cell, widths of the bit line and the word line being chosen to reduce current-resistance drop.

公开(公告)号：US20240112730A1

公开(公告)日：2024-04-04

申请号：US17957945

申请日：2022-09-30

Applicant: Intel Corporation

Inventor： Sou-Chi Chang ,  Nazila Haratipour ,  Saima Siddiqui ,  Uygar Avci ,  Chia-Ching Lin

IPC: G11C13/00 ,  G11C11/22 ,  H01L45/00

CPC classification number: G11C13/0026 ,  G11C11/22 ,  G11C13/0007 ,  G11C13/0028 ,  G11C13/0033 ,  G11C13/004 ,  G11C13/0069 ,  H01L45/1233 ,  H01L45/1253 ,  H01L45/146 ,  G11C2213/79

Abstract: Techniques and mechanisms for storing data with a memory cell which comprises a ferroelectric (FE) resistive junction. In an embodiment, a memory cell comprises a transistor and a FE resistive junction structure which is coupled to the transistor. The FE resistive junction structure comprises electrode structures, and a layer of a material which is between said electrode structures, wherein the material is a FE oxide or a FE semiconductor. The FE resistive junction structure selectively provides any of various levels of resistance, each to represent a respective one or more bits. A current flow through the FE resistive junction structure is characterized by thermionic emission through a Schottky barrier at an interface with one of the electrode structures. In another embodiment, the FE resistive junction structure further comprises one or more dielectric layers each between the layer of material and a different respective one of the electrode structures.

公开(公告)号：US11908514B2

公开(公告)日：2024-02-20

申请号：US17667080

申请日：2022-02-08

Applicant: STMicroelectronics (Grenoble 2) SAS ,  STMicroelectronics S.r.l.

Inventor： Antonino Conte ,  Alin Razafindraibe ,  Francesco Tomaiuolo ,  Thibault Mortier

IPC: G11C13/00

CPC classification number: G11C13/0028 ,  G11C13/003 ,  G11C13/0004 ,  G11C2213/79

Abstract: In an embodiment, a non-volatile memory device includes a memory array including a plurality of memory portions, each memory portion having a respective plurality of memory cells arranged in rows and columns, wherein the memory portions are arranged in groups, each group of memory portions having a plurality of respective memory portions arranged in a row and a plurality of respective wordlines that extend through the respective memory portions, and wherein the memory cells of the memory portions of the group are coupled to the respective wordlines and a row decoder including a pre-decoding stage configured to execute a selection, in which it selects a wordline that extends through a group of memory portions and deselects other wordlines that extend through the group of memory portions, and a subsequent deselection, in which it deselects all the wordlines that extend through the group of memory portions, wherein the row decoder further includes, for each group of memory portions, a shared pull-up stage configured to decouple from or couple to a node at a first reference potential each wordline that extends through the group of memory portions, when the wordline is respectively selected or deselected, so as to impose on each wordline, when deselected, a deselection voltage, a plurality of pull-down stages distributed along the group of memory portions, each pull-down stage being configured to locally couple each wordline that extends through the group of memory portions, when selected, to a node at a second reference potential, so as to impose locally a selection voltage on the wordline, wherein each pull-down stage is further configured to locally decouple from the node at the second reference potential each wordline that extends through the group of memory portions, when deselected; and a number of local pull-up stages distributed along the group of memory portions, each local pull-up stage having, for each wordline that extends through the group of memory portions, a corresponding local pull-up transistor of an NMOS type.

公开(公告)号：US11848050B2

公开(公告)日：2023-12-19

申请号：US17829571

申请日：2022-06-01

Applicant: HEFEI RELIANCE MEMORY LIMITED

Inventor： Brent Steven Haukness

IPC: G11C13/00 ,  G11C8/08

CPC classification number: G11C13/0069 ,  G11C13/004 ,  G11C13/0007 ,  G11C13/0028 ,  G11C13/0097 ,  G11C8/08 ,  G11C2013/0045 ,  G11C2013/0071 ,  G11C2013/0078 ,  G11C2213/79

Abstract: The gate of the access transistor of a 1 transistor 1 resistor (1T1R) type RRAM cell is biased relative to the source of the access transistor using a current mirror. Under the influence of a voltage applied across the 1T1R cell (e.g., via the bit line), the RRAM memory element switches from a higher resistance to a lower resistance. As the RRAM memory element switches from the higher resistance to the lower resistance, the current through the RRAM cell switches from being substantially determined by the higher resistance of the RRAM device (while the access transistor is operating in the linear region) to being substantially determined by the saturation region operating point of the access transistor.

公开(公告)号：US20230377648A1

公开(公告)日：2023-11-23

申请号：US18362863

申请日：2023-07-31

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Chin-I SU ,  Chung-Cheng CHOU ,  Yu-Der CHIH ,  Zheng-Jun LIN

IPC: G11C13/00

CPC classification number: G11C13/0069 ,  G11C13/0028 ,  G11C13/0038 ,  G11C2213/79 ,  G11C2013/0078

Abstract: A method of operating a memory circuit includes generating a first current in response to a first voltage. The first current includes a first set of leakage currents and a first write current. The method further includes generating, by a tracking circuit, a second set of leakage currents configured to track the first set of leakage currents of the first column of memory cells, and mirroring the first current in a first path with a second current in a second path by a first current mirror. The second current includes the second set of leakage currents and a second write current. The first write current corresponds to the second write current. The first set of leakage currents corresponds to the second set of leakage currents.

公开(公告)号：US11825665B2

公开(公告)日：2023-11-21

申请号：US17949436

申请日：2022-09-21

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Shunpei Yamazaki ,  Jun Koyama ,  Kiyoshi Kato

IPC: H01L29/78 ,  H10B99/00 ,  H01L27/105 ,  H01L27/12 ,  H10B12/00 ,  H10B41/20 ,  H10B41/70 ,  H01L29/24 ,  H01L29/786 ,  G11C13/00 ,  H01L49/02 ,  H10B10/00

CPC classification number: H10B99/00 ,  H01L27/105 ,  H01L27/124 ,  H01L27/1225 ,  H01L27/1255 ,  H01L29/24 ,  H01L29/7869 ,  H01L29/78696 ,  H10B12/00 ,  H10B41/20 ,  H10B41/70 ,  G11C13/003 ,  G11C13/0007 ,  G11C2213/79 ,  H01L28/40 ,  H10B10/00

Abstract: An object of one embodiment of the present invention is to provide a semiconductor device with a novel structure in which stored data can be stored even when power is not supplied in a data storing time and there is no limitation on the number of times of writing. The semiconductor device includes a first transistor which includes a first channel formation region using a semiconductor material other than an oxide semiconductor, a second transistor which includes a second channel formation region using an oxide semiconductor material, and a capacitor. One of a second source electrode and a second drain electrode of the second transistor is electrically connected to one electrode of the capacitor.

公开(公告)号：US20230354618A1

公开(公告)日：2023-11-02

申请号：US18347794

申请日：2023-07-06

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Chin-Chieh Yang ,  Chih-Yang Chang ,  Wen-Ting Chu ,  Yu-Wen Liao

IPC: H10B63/00 ,  G11C13/00 ,  H10N70/20 ,  H10N70/00

CPC classification number: H10B63/82 ,  G11C13/0011 ,  G11C13/0069 ,  H10B63/30 ,  H10B63/80 ,  H10N70/20 ,  H10N70/24 ,  H10N70/063 ,  H10N70/826 ,  H10N70/841 ,  H10N70/8833 ,  H10N70/8836 ,  G11C13/0023 ,  G11C13/004 ,  G11C2213/79 ,  H01L23/5226

Abstract: The present disclosure, in some embodiments, relates to an integrated chip. The integrated chip includes a first resistive random access memory (RRAM) element and a second RRAM element over a substrate. A conductive element is arranged below the first RRAM element and the second RRAM element. The conductive element electrically couples the first RRAM element to the second RRAM element. An upper insulating layer continuously extends over the first RRAM element and the second RRAM element. An upper inter-level dielectric (ILD) structure laterally surrounds the first RRAM element and the second RRAM element. The upper insulating layer separates the first RRAM element and the second RRAM element from the upper ILD structure.

公开(公告)号：US20230306245A1

公开(公告)日：2023-09-28

申请号：US17703889

申请日：2022-03-24

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Jen-Chieh LIU ,  Win-San KHWA ,  Jui-Jen WU ,  Meng-Fan CHANG

IPC: G06N3/063 ,  G11C13/00 ,  G11C11/54

CPC classification number: G06N3/063 ,  G11C13/0004 ,  G11C13/0069 ,  G11C13/0061 ,  G11C13/0097 ,  G11C13/003 ,  G11C11/54 ,  G11C2213/79

Abstract: A programming circuit includes a time difference converter circuit and a pulse generator circuit. The converter circuit is configured to receive a first pulse from a first neuron device and a second pulse from a second neuron device, and to output a time difference signal corresponding to a time difference between the first pulse and the second pulse. The pulse generator circuit includes an input coupled to the output of the time difference converter circuit to receive the time difference signal, and an output at which the pulse generator circuit is configured to output a program voltage corresponding to the time difference signal. The output of the pulse generator circuit is configured to be coupled to a synapse device coupled between the first neuron device and the second neuron device to program a weight value in the synapse device with the program voltage.