公开(公告)号：US20250069632A1

公开(公告)日：2025-02-27

申请号：US18787812

申请日：2024-07-29

Applicant: Micron Technology, Inc.

Inventor： Leon Zlotnik

IPC: G11C7/22 ,  G11C7/10

Abstract: An example method for critical timing driven adjustable voltage frequency scaling can include performing sensing operations on a system on chip (SoC) at a respective plurality of time windows each associated with a particular data value, comparing at least two of the particular data values associated with at least two respective time windows of the plurality of time windows, in response to the at least two of the particular data values being a same data value, determining that a clock margin is above a threshold clock margin, and determining that a clock margin is below a threshold clock margin. In some instance, in response to determining that the clock margin is above the threshold clock margin, a clocking of the SoC can be adjusted, a voltage of at least one operation of the SoC can be adjusted, and/or a clocking frequency of at least one operation of the SoC, among other possibilities.

公开(公告)号：US20250069631A1

公开(公告)日：2025-02-27

申请号：US18771448

申请日：2024-07-12

Applicant: Micron Technology, Inc.

Inventor： Martin Bach ,  Miljana Nenadovic ,  Hemant Madhewar ,  Mani Balakrishnan ,  Thomas Hein ,  Martin Brox

IPC: G11C7/22 ,  G11C7/10

Abstract: Methods, systems, and devices for data alignment for memory are described. A memory device may implement individual time adjustments to align portions of a multilevel signal modulated by a modulation scheme with three levels. In some cases, signal paths for generating and transmitting the portions of the multilevel signal may reference a clock signal, and adjustable delay circuits may apply individual delays to the clock signal received at each signal path. For example, a first adjustable delay circuit may apply a first time adjustment to the clock signal received at a first signal path for generating a first portion. And, a second adjustable delay circuit may apply a second time adjustment to the clock signal received at a second signal path for generating a second portion. Applying the time adjustments to the signal paths may align the portions of the multilevel signal in time, compared to the clock signal.

公开(公告)号：US20250069629A1

公开(公告)日：2025-02-27

申请号：US18786480

申请日：2024-07-27

Applicant: Micron Technology, Inc.

Inventor： Dmitri Yudanov ,  James B. Johnson ,  Peter L. Brown ,  Glen E. Hush

IPC: G11C7/10 ,  G11C7/08 ,  G11C7/22

Abstract: Processing can occur in registers of a memory sub-system. A first plurality of registers coupled to the plurality of sense amplifiers can store the first plurality of bits received from the plurality of sense amplifiers. Processing circuitry coupled to the first plurality of registers can receive the first plurality of bits from the first plurality of registers and can perform an operation on the first plurality of bits to generate result bits. A second plurality of registers coupled to the processing circuitry and the plurality of registers can store the result bits received from the processing circuitry and can provide the result bits to a plurality of data input/output (I/O) lines prior to storing a second plurality of bits.

公开(公告)号：US20250069628A1

公开(公告)日：2025-02-27

申请号：US18943250

申请日：2024-11-11

Applicant: SK hynix Inc.

Inventor： Byoung Sung YOU

IPC: G11C7/10 ,  G06F11/10 ,  G11C7/12 ,  G11C29/42

Abstract: A semiconductor device includes a memory cell array and a plurality of read and write circuits. The memory cell array includes a plurality of planes. Any one of the read and write circuits generates parity data based on data sequentially received from a controller through a channel.

公开(公告)号：US12237040B2

公开(公告)日：2025-02-25

申请号：US17468210

申请日：2021-09-07

Applicant: Intel Corporation

Inventor： Sourabh Dongaonkar ,  Chetan Chauhan ,  Jawad B. Khan ,  Sandeep K. Guliani ,  William K. Waller

IPC: G11C7/10 ,  G11C5/02 ,  G11C5/14

Abstract: A memory accessed by rows and/or by columns in which an array of bits can be physically stored in multi-bit wide columns in physically contiguous rows is provided. A multi-bit wide logical column is arranged diagonally across (M/multi-bits) physical rows and (M/multi-bits) physical columns with each of the plurality of multi-bit wide logical columns in the logical row stored in a different physical row and physical multi-bit column.

公开(公告)号：US20250061930A1

公开(公告)日：2025-02-20

申请号：US18751094

申请日：2024-06-21

Applicant: Micron Technology, Inc.

Inventor： Hernan Castro

IPC: G11C7/16 ,  G11C7/10 ,  G11C7/12 ,  G11C8/08

Abstract: A memory sub-system configured to perform multiplication and accumulation operations using truncated outputs. For example, voltages can be applied, according to a bit slice having a slice weight in an input, to memory cells storing weights. A resolution control can be applied, according to the slice weight, to an analog to digital converter coupled to the line having a current resulting from the memory cells responsive to the voltages. The analog to digital converter can measure at least one first bit of a quantity representative of a magnitude of the current in the line to provide a truncated output, skipping measuring of at least one second bit of the quantity according to the resolution control. Summing truncated outputs resulting from the bit slices from the input can provide an approximated result of the sum of elements in the input weighted by the weights.

公开(公告)号：US20250061928A1

公开(公告)日：2025-02-20

申请号：US18936298

申请日：2024-11-04

Applicant: Micron Technology, Inc.

Inventor： Murong Lang ,  Zhenming Zhou ,  Jian Huang ,  Zhongguang Xu ,  Jiangli Zhu

IPC: G11C7/10

Abstract: A read operation is performed on a set of memory cells addressable by a first wordline (WL), wherein the set of memory cells is comprised by an open translation unit (TU_ of memory cells of a memory device. Respective threshold voltage offset bins for each WL of a second plurality of WLs coupled to respective sets of memory cells comprised by the open TU are determined based on a threshold voltage offset bin associated with the first WL. Respective default threshold voltages for each WL of the first plurality of WLs are updated based on the respective threshold voltage offset bins for each WL of the second plurality of WLs.

公开(公告)号：US12230354B2

公开(公告)日：2025-02-18

申请号：US17971300

申请日：2022-10-21

Applicant: Lodestar Licensing Group LLC

Inventor： Jason T. Zawodny ,  Kelley D. Dobelstein ,  Timothy P. Finkbeiner ,  Richard C. Murphy

IPC: G11C7/10 ,  G06F3/06 ,  G11C7/06 ,  G11C8/12 ,  G11C11/408 ,  G11C11/4091 ,  G11C11/4096

Abstract: The present disclosure includes apparatuses and methods related to scatter/gather in a memory device. An example apparatus comprises a memory device that includes an array of memory cells, sensing circuitry, and a memory controller coupled to one another. The sensing circuitry includes a sense amplifier and a compute component configured to implement logical operations. A channel controller is configured to receive a block of instructions, the block of instructions including individual instructions for at least one of a gather operation and a scatter operation. The channel controller is configured to send individual instructions to the memory device and to control the memory controller such that the at least one of the gather operation and the scatter operation is executed on the memory device based on a corresponding one of the individual instructions.

公开(公告)号：US20250055459A1

公开(公告)日：2025-02-13

申请号：US18792735

申请日：2024-08-02

Applicant: Samsung Electronics Co., Ltd.

Inventor： Moon-Chul Choi ,  Sung-Yong Cho

IPC: H03K19/00 ,  G11C7/10 ,  H04L25/03

Abstract: An integrated circuit device may include a transmission driver and an equalizer. The transmission driver may be configured to, in response to a transmission control data, transmit an output signal to an outside through a signal line in a transmission operation that outputs the output signal to the outside, and provide termination resistance in a reception operation that receives an input signal from the outside through the signal line. The equalizer may be configured to, in response to an equalizer control data, amplify high-frequency components of the output signal in the transmission operation, and to provide termination resistance in the reception operation.

公开(公告)号：US20250054527A1

公开(公告)日：2025-02-13

申请号：US18806285

申请日：2024-08-15

Applicant: Micron Technology, Inc.

Inventor： Cheng Cheng Ang ,  Chun Lei Kong ,  Ting Luo ,  Aik Boon Edmund Yap

IPC: G11C7/10 ,  G06F12/02 ,  G11C8/08 ,  G11C29/12

Abstract: Methods, systems, and devices for skipping pages for weak wordlines of a memory device during pre-programming are described. A memory device may be configured to operate in a first mode involving skipping one or more pages (e.g., a lower page (LP)) associated with a set of wordlines. In some examples, a testing system may determine the set of wordlines (e.g., weak wordlines) for which to skip pages according to performance degradation for the wordlines in response to applying a threshold temperature to a test memory device. In the first mode, the memory device may store (e.g., pre-program) data in a subset of pages distinct from the skipped pages. The memory device may switch to a second mode in response to a trigger condition. In the second mode, the memory device may use each page associated with the wordlines and may refrain from skipping the one or more pages.