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公开(公告)号:US20240256156A1
公开(公告)日:2024-08-01
申请号:US18402990
申请日:2024-01-03
发明人: Glen E. Hush
IPC分类号: G06F3/06
CPC分类号: G06F3/0626 , G06F3/0629 , G06F3/0673
摘要: Methods, systems, and devices related to sense amplifiers of a memory device serving as a Static Random Access Memory (SRAM) resource. For example, a memory array of a memory device can be coupled to sense amplifiers. The sense amplifiers can be electrically disconnected from digit lines of the memory array. Data can be stored in the sense amplifiers. The data can be communicated from the sense amplifiers to a processing device external to the memory array and the sense amplifiers. The sense amplifiers can receive data from the processing device and, when electrically disconnected from the number of digit lines, store the received data.
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公开(公告)号:US11954499B2
公开(公告)日:2024-04-09
申请号:US17885143
申请日:2022-08-10
IPC分类号: G06F9/4401 , G06F9/38 , G06F12/0868 , G06F12/1045 , G06F13/16
CPC分类号: G06F9/4403 , G06F9/3836 , G06F9/4406 , G06F12/0868 , G06F12/1054 , G06F13/1668 , G06F2212/7201 , G06F2212/7211
摘要: Methods, systems, and devices for operational code storage for an on-die microprocessor are described. A microprocessor may be formed on-die with a memory array. Operating code for the microprocessor may be stored in the memory array, possibly along with other data (e.g., tracking or statistical data) used or generated by the on-die microprocessor. A wear leveling algorithm may result in some number of rows within the memory array not being used to store user data at any given time, and these rows may be used to store the operating code and possibly other data for the on-die microprocessor. The on-die microprocessor may boot and run based on the operating code stored in memory array.
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公开(公告)号:US11915742B2
公开(公告)日:2024-02-27
申请号:US17885242
申请日:2022-08-10
IPC分类号: G06F13/00 , G11C11/4093 , G06F13/16 , G06F3/06 , G11C11/4096 , H01L23/00 , H01L25/065 , H01L21/78 , H01L21/66 , H01L25/18 , H01L25/00 , G11C7/08 , G11C7/10 , G11C11/408 , G11C11/4091 , G16B50/10 , G16B30/00 , G06F13/28
CPC分类号: G11C11/4093 , G06F3/0656 , G06F13/1673 , G06F13/28 , G11C7/08 , G11C7/1039 , G11C11/4087 , G11C11/4091 , G11C11/4096 , G16B30/00 , G16B50/10 , H01L21/78 , H01L22/12 , H01L24/08 , H01L24/48 , H01L24/80 , H01L25/0652 , H01L25/0657 , H01L25/18 , H01L25/50 , G06F2213/28 , H01L24/16 , H01L2224/0801 , H01L2224/08145 , H01L2224/1601 , H01L2224/16221 , H01L2224/48091 , H01L2224/48145 , H01L2224/48221 , H01L2224/80895 , H01L2224/80896 , H01L2225/06517 , H01L2225/06524 , H01L2225/06527 , H01L2225/06541 , H01L2225/06565 , H01L2225/06589 , H01L2924/1431 , H01L2924/1436 , H01L2924/14335
摘要: A wafer-on-wafer formed memory and logic device can enable high bandwidth transmission of data directly between a memory die and a logic die. A logic die that is bonded to a memory die via a wafer-on-wafer bonding process can receive signals indicative of a genetic sequence from the memory die and through a wafer-on-wafer bond. The logic die can also perform a genome annotation lotic operation to attach biological information to the genetic sequence. An annotated genetic sequence can be provided as an output.
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公开(公告)号:US11782721B2
公开(公告)日:2023-10-10
申请号:US17680538
申请日:2022-02-25
发明人: Glen E. Hush , Aaron P. Boehm , Fa-Long Luo
CPC分类号: G06F9/3855 , G06F9/3001 , G06F9/30018 , G11C7/08 , G11C7/1006 , G06F9/30032
摘要: Systems, apparatuses, and methods for organizing bits in a memory device are described. In a number of embodiments, an apparatus can include an array of memory cells, a data interface, a multiplexer coupled between the array of memory cells and the data interface, and a controller coupled to the array of memory cells, the controller configured to cause the apparatus to latch bits associated with a row of memory cells in the array in a number of sense amplifiers in a prefetch operation and send the bits from the sense amplifiers, through a multiplexer, to a data interface, which may include or be referred to as DQs. The bits may be sent to the DQs in a particular order that may correspond to a particular matrix configuration and may thus facilitate or reduce the complexity of arithmetic operations performed on the data.
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公开(公告)号:US11768614B2
公开(公告)日:2023-09-26
申请号:US17169138
申请日:2021-02-05
IPC分类号: G06F12/00 , G06F3/06 , G06F12/0868 , G06F12/02
CPC分类号: G06F3/0626 , G06F3/061 , G06F3/064 , G06F3/0631 , G06F3/0658 , G06F3/0661 , G06F12/0246 , G06F12/0868 , G06F2212/1016
摘要: Systems, apparatuses, and methods related to storage device operation orchestration are described. A plurality of computing devices (or “tiles”) can be coupled to a controller (e.g., an “orchestration controller”) and an interface. The controller can control operation of the computing devices. For instance, the controller can include circuitry to request a block of data from a memory device coupled to the apparatus, cause a processing unit of at least one computing device of the plurality of computing devices to perform an operation on the block of data in which at least some of the data is ordered, reordered, removed, or discarded, and cause, after some of the data is ordered, reordered, removed, or discarded, the block of data to be transferred to the interface coupled to the plurality of computing devices.
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公开(公告)号:US11751031B2
公开(公告)日:2023-09-05
申请号:US17708781
申请日:2022-03-30
发明人: Fa-Long Luo , Glen E. Hush , Aaron P. Boehm
IPC分类号: G06F3/06 , H04W4/70 , H04W72/04 , H04W72/12 , H04W74/02 , H04W74/04 , H04W74/08 , H04W76/14 , H04W88/06 , H04W92/18 , H04W72/0453 , H04W72/23
CPC分类号: H04W4/70 , G06F3/061 , G06F3/0659 , G06F3/0673 , H04W72/0453 , H04W72/12 , H04W72/1215 , H04W72/23 , H04W74/02 , H04W74/04 , H04W74/08 , H04W76/14 , H04W88/06 , H04W92/18
摘要: Methods, apparatuses, and systems related to wireless main memory for computing are described. A device may include a processor that is wirelessly coupled to a memory array, which may be in a physically separate device. The processor may execute instructions stored in and wirelessly communicated from the memory array. The processor may read data from or write data to the memory array via a wireless communication link (e.g., using resources of an ultra high frequency, super high frequency, and/or extremely high frequency band). Several devices may have a small amount of local memory (or no local memory) and may share, via a wireless communication link, a main memory array. Memory devices may include memory resources and transceiver resources; they may be configured to use one or several communication protocols over licensed or shared frequency spectrum bands, directly (e.g., device-to-device) or indirectly (e.g., via a base station).
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公开(公告)号:US20230236752A1
公开(公告)日:2023-07-27
申请号:US18125625
申请日:2023-03-23
发明人: Perry V. Lea , Glen E. Hush
IPC分类号: G06F3/06 , G11C7/10 , G11C11/4076 , G11C11/4091 , G11C11/4097
CPC分类号: G06F3/0647 , G11C7/1006 , G11C11/4076 , G11C11/4091 , G11C11/4097 , G06F3/061 , G06F3/0625 , G06F3/0685 , G11C7/1072 , G11C2207/2236 , G11C2207/2245
摘要: The present disclosure includes apparatuses and methods for data movement. An example apparatus includes a memory device that includes a plurality of subarrays of memory cells and sensing circuitry coupled to the plurality of subarrays. The sensing circuitry includes a sense amplifier and a compute component. The memory device also includes a plurality of subarray controllers. Each subarray controller of the plurality of subarray controllers is coupled to a respective subarray of the plurality of subarrays and is configured to direct performance of an operation with respect to data stored in the respective subarray of the plurality of subarrays. The memory device is configured to move a data value corresponding to a result of an operation with respect to data stored in a first subarray of the plurality of subarrays to a memory cell in a second subarray of the plurality of subarrays.
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公开(公告)号:US11682449B2
公开(公告)日:2023-06-20
申请号:US17322442
申请日:2021-05-17
发明人: Glen E. Hush , Richard C. Murphy
IPC分类号: G11C5/06 , G11C11/4093 , G11C11/4091 , G11C5/02 , G11C7/10
CPC分类号: G11C11/4093 , G11C5/025 , G11C7/1006 , G11C11/4091 , G11C7/106 , G11C2207/2245
摘要: The present disclosure includes apparatuses and methods for compute in data path. An example apparatus includes an array of memory cells. Sensing circuitry is coupled to the array of memory cells. A shared input/output (I/O) line provides a data path associated with the array. The shared I/O line couples the sensing circuitry to a compute component in the data path of the shared I/O line.
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公开(公告)号:US11425740B2
公开(公告)日:2022-08-23
申请号:US16989051
申请日:2020-08-10
发明人: Fa-Long Luo , Glen E. Hush , Aaron P. Boehm
摘要: Systems, apparatuses and method related to remotely executable instructions are described. A device may be wirelessly coupled to (e.g., physically separated) another device, which may be in a physically separate device. The another device may remotely execute instructions associated with performing various operations, which would have been entirely executed at the device absent the another device. The outputs obtained as a result of the execution may be transmitted, via the transceiver, back to the device via a wireless communication link (e.g., using resources of an ultra high frequency (UHF), super high frequency (SHF), extremely high frequency (EHF), and/or tremendously high frequency (THF) bands). The another device at which the instructions are remotely executable may include memory resources, processing resources, and transceiver resources; they may be configured to use one or several communication protocols over licensed or shared frequency spectrum bands, directly (e.g., device-to-device) or indirectly (e.g., via a base station).
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公开(公告)号:US11372585B2
公开(公告)日:2022-06-28
申请号:US16866740
申请日:2020-05-05
发明人: Glen E. Hush , Richard C. Murphy , Honglin Sun
摘要: Apparatuses and methods can be related to generating an asynchronous process topology in a memory device. The topology can be generated based on results of a number of processes. The processes can be asynchronous given that a processing resource that implement the processes do not use a clock signal to generate the topology.
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