公开(公告)号：US20230333744A1

公开(公告)日：2023-10-19

申请号：US18211356

申请日：2023-06-19

Applicant: Micron Technology, Inc.

Inventor： Jason T. Zawodny ,  Glen E. Hush ,  Troy A. Manning ,  Timothy P. Finkbeiner

IPC: G11C8/12 ,  G11C7/10 ,  G06F15/78 ,  G06F3/06 ,  G11C29/28

CPC classification number: G06F3/0611 ,  G06F3/0625 ,  G06F3/0659 ,  G06F3/0683 ,  G06F15/7821 ,  G11C7/10 ,  G11C7/1006 ,  G11C8/12 ,  G11C29/28 ,  G11C2029/2602

Abstract: The present disclosure includes apparatuses and methods for parallel writing to multiple memory device locations. An example apparatus comprises a memory device. The memory device includes an array of memory cells and sensing circuitry coupled to the array. The sensing circuitry includes a sense amplifier and a compute component configured to implement logical operations. A memory controller in the memory device is configured to receive a block of resolved instructions and/or constant data from the host. The memory controller is configured to write the resolved instructions and/or constant data in parallel to a plurality of locations the memory device.

公开(公告)号：US11726791B2

公开(公告)日：2023-08-15

申请号：US17743062

申请日：2022-05-12

Applicant: Micron Technology, Inc.

Inventor： Kyle B. Wheeler ,  Richard C. Murphy ,  Troy A. Manning ,  Dean A. Klein

IPC: G06F9/38 ,  G06F15/78 ,  G11C7/06 ,  G11C7/10 ,  G11C11/408 ,  G11C11/4096

CPC classification number: G06F9/3877 ,  G06F15/7821 ,  G11C7/06 ,  G11C7/065 ,  G11C7/1006 ,  G11C7/1036 ,  G11C11/4087 ,  G11C11/4096

Abstract: Examples of the present disclosure provide apparatuses and methods related to generating and executing a control flow. An example apparatus can include a first device configured to generate control flow instructions, and a second device including an array of memory cells, an execution unit to execute the control flow instructions, and a controller configured to control an execution of the control flow instructions on data stored in the array.

公开(公告)号：US20230033704A1

公开(公告)日：2023-02-02

申请号：US17885143

申请日：2022-08-10

Applicant: Micron Technology, Inc.

Inventor： Troy A. Manning ,  Jonathan D. Harms ,  Troy D. Larsen ,  Glen E. Hush ,  Timothy P. Finkbeiner

IPC: G06F9/4401 ,  G06F9/38 ,  G06F12/0868 ,  G06F13/16 ,  G06F12/1045

Abstract: Methods, systems, and devices for operational code storage for an on-die microprocessor are described. A microprocessor may be formed on-die with a memory array. Operating code for the microprocessor may be stored in the memory array, possibly along with other data (e.g., tracking or statistical data) used or generated by the on-die microprocessor. A wear leveling algorithm may result in some number of rows within the memory array not being used to store user data at any given time, and these rows may be used to store the operating code and possibly other data for the on-die microprocessor. The on-die microprocessor may boot and run based on the operating code stored in memory array.

公开(公告)号：US20220343969A1

公开(公告)日：2022-10-27

申请号：US17859992

申请日：2022-07-07

Applicant: Micron Technology, Inc.

Inventor： Troy A. Manning ,  Glen E. Hush

IPC: G11C11/4091 ,  G11C11/4097 ,  H03K19/20 ,  H03K19/0948 ,  G11C7/10

Abstract: The present disclosure includes apparatuses and methods related to logical operations using memory cells. An example apparatus comprises a first memory cell controlled to invert a data value stored therein and a second memory cell controlled to invert a data value stored therein. The apparatus may further include a controller coupled to the first memory cell and the second memory cell. The controller may be configured to cause performance of a logical operation between the data value stored in the first memory cell and the data value stored in the second memory cell.

公开(公告)号：US11422826B2

公开(公告)日：2022-08-23

申请号：US16878226

申请日：2020-05-19

Applicant: Micron Technology, Inc.

Inventor： Troy A. Manning ,  Jonathan D. Harms ,  Troy D. Larsen ,  Glen E. Hush ,  Timothy P. Finkbeiner

IPC: G06F9/4401 ,  G06F9/38 ,  G06F12/0868 ,  G06F13/16 ,  G06F12/1045

Abstract: Methods, systems, and devices for operational code storage for an on-die microprocessor are described. A microprocessor may be formed on-die with a memory array. Operating code for the microprocessor may be stored in the memory array, possibly along with other data (e.g., tracking or statistical data) used or generated by the on-die microprocessor. A wear leveling algorithm may result in some number of rows within the memory array not being used to store user data at any given time, and these rows may be used to store the operating code and possibly other data for the on-die microprocessor. The on-die microprocessor may boot and run based on the operating code stored in memory array.

公开(公告)号：US11334362B2

公开(公告)日：2022-05-17

申请号：US17027431

申请日：2020-09-21

Applicant: Micron Technology, Inc.

Inventor： Kyle B. Wheeler ,  Richard C. Murphy ,  Troy A. Manning ,  Dean A. Klein

IPC: G06F9/38 ,  G06F15/78 ,  G11C7/06 ,  G11C7/10 ,  G11C11/408 ,  G11C11/4096

Abstract: Examples of the present disclosure provide apparatuses and methods related to generating and executing a control flow. An example apparatus can include a first device configured to generate control flow instructions, and a second device including an array of memory cells, an execution unit to execute the control flow instructions, and a controller configured to control an execution of the control flow instructions on data stored in the array.

公开(公告)号：US20210065778A1

公开(公告)日：2021-03-04

申请号：US17098160

申请日：2020-11-13

Applicant: Micron Technology, Inc.

Inventor： Kyle B. Wheeler ,  Troy A. Manning ,  Richard C. Murphy

IPC: G11C11/4091 ,  G11C7/06 ,  G11C7/10 ,  G11C11/4076 ,  G11C11/4093 ,  G11C11/408 ,  G11C11/4096

Abstract: One example of the present disclosure includes performing a comparison operation in memory using a logical representation of a first value stored in a first portion of a number of memory cells coupled to a sense line of a memory array and a logical representation of a second value stored in a second portion of the number of memory cells coupled to the sense line of the memory array. The comparison operation compares the first value to the second value, and the method can include storing a logical representation of a result of the comparison operation in a third portion of the number of memory cells coupled to the sense line of the memory array.

公开(公告)号：US20210020207A1

公开(公告)日：2021-01-21

申请号：US17063495

申请日：2020-10-05

Applicant: Micron Technology, Inc.

Inventor： Perry V. Lea ,  Troy A. Manning

IPC: G11C7/10 ,  H03K19/173 ,  G06F13/12 ,  G11C11/408 ,  G11C8/12 ,  G11C11/4096

Abstract: The present disclosure includes apparatuses and methods for bank to bank data transfer. An example apparatus includes a plurality of banks of memory cells, an internal bus configured to transfer data between the plurality of banks and an external bus interface, and a bank-to-bank transfer bus configured to transfer data between the plurality of banks.

公开(公告)号：US10734038B2

公开(公告)日：2020-08-04

申请号：US16277472

申请日：2019-02-15

Applicant: Micron Technology, Inc.

Inventor： Glen E. Hush ,  Troy A. Manning

IPC: G11C7/00 ,  G11C7/10 ,  G11C11/4091 ,  G11C11/4093 ,  G11C11/16 ,  G11C7/06

Abstract: The present disclosure includes apparatuses and methods related to performing logical operations using sensing circuitry. An example apparatus comprises an array of memory cells and sensing circuitry coupled to the array. The sensing circuitry includes a sense amplifier coupled to a pair of complementary sense lines, and a compute component coupled to the sense amplifier. The compute component includes a dynamic latch. The sensing circuitry is configured to perform a logical operation and initially store the result in the sense amplifier.

公开(公告)号：US10664345B2

公开(公告)日：2020-05-26

申请号：US16050585

申请日：2018-07-31

Applicant: Micron Technology, Inc.

Inventor： Troy A. Manning ,  Troy D. Larsen ,  Martin L. Culley

IPC: G06F11/10 ,  G06F3/06 ,  G11C29/52 ,  G06F8/41

Abstract: The present disclosure includes apparatuses and methods for physical page, logical page, and codeword correspondence. A number of methods include error coding a number of logical pages of data as a number of codewords and writing the number of codewords to a number of physical pages of memory. The number of logical pages of data can be different than the number of physical pages of memory.