公开(公告)号：US20240403158A1

公开(公告)日：2024-12-05

申请号：US18673225

申请日：2024-05-23

Applicant: Micron Technology, Inc.

Inventor： Sukneet Singh Basuta ,  Shashank Bangalore Lakshman ,  Jonathan D. Harms ,  Jonathan J. Strand

IPC: G06F11/07 ,  G06F11/10 ,  G06F12/10 ,  G11C11/22

Abstract: Methods, systems, and devices for imprint recovery management for memory systems are described. In some cases, memory cells may become imprinted, which may refer to conditions where a cell becomes predisposed toward storing one logic state over another, resistant to being written to a different logic state, or both. Imprinted memory cells may be recovered using a recovery or repair process that may be initiated according to various conditions, detections, or inferences. In some examples, a system may be configured to perform imprint recovery operations that are scaled or selected according to a characterized severity of imprint, an operational mode, environmental conditions, and other factors. Imprint management techniques may increase the robustness, accuracy, or efficiency with which a memory system, or components thereof, can operate in the presence of conditions associated with memory cell imprinting.

公开(公告)号：US20230033704A1

公开(公告)日：2023-02-02

申请号：US17885143

申请日：2022-08-10

Applicant: Micron Technology, Inc.

Inventor： Troy A. Manning ,  Jonathan D. Harms ,  Troy D. Larsen ,  Glen E. Hush ,  Timothy P. Finkbeiner

IPC: G06F9/4401 ,  G06F9/38 ,  G06F12/0868 ,  G06F13/16 ,  G06F12/1045

Abstract: Methods, systems, and devices for operational code storage for an on-die microprocessor are described. A microprocessor may be formed on-die with a memory array. Operating code for the microprocessor may be stored in the memory array, possibly along with other data (e.g., tracking or statistical data) used or generated by the on-die microprocessor. A wear leveling algorithm may result in some number of rows within the memory array not being used to store user data at any given time, and these rows may be used to store the operating code and possibly other data for the on-die microprocessor. The on-die microprocessor may boot and run based on the operating code stored in memory array.

公开(公告)号：US11422826B2

公开(公告)日：2022-08-23

申请号：US16878226

申请日：2020-05-19

Applicant: Micron Technology, Inc.

Inventor： Troy A. Manning ,  Jonathan D. Harms ,  Troy D. Larsen ,  Glen E. Hush ,  Timothy P. Finkbeiner

IPC: G06F9/4401 ,  G06F9/38 ,  G06F12/0868 ,  G06F13/16 ,  G06F12/1045

Abstract: Methods, systems, and devices for operational code storage for an on-die microprocessor are described. A microprocessor may be formed on-die with a memory array. Operating code for the microprocessor may be stored in the memory array, possibly along with other data (e.g., tracking or statistical data) used or generated by the on-die microprocessor. A wear leveling algorithm may result in some number of rows within the memory array not being used to store user data at any given time, and these rows may be used to store the operating code and possibly other data for the on-die microprocessor. The on-die microprocessor may boot and run based on the operating code stored in memory array.

公开(公告)号：US20220261062A1

公开(公告)日：2022-08-18

申请号：US17740130

申请日：2022-05-09

Applicant: Micron Technology, Inc.

Inventor： Jonathan D. Harms

IPC: G06F1/3234 ,  G06F1/08 ,  G06F1/324 ,  G06F11/34 ,  G06F11/30 ,  G06F11/00 ,  G06F1/3206

Abstract: Methods and apparatus for using characterized devices such as memories. In one embodiment, characterized memories are associated with a range of performances over a range of operational parameters. The characterized memories can be used in conjunction with a solution density function to optimize memory searching. In one exemplary embodiment, a cryptocurrency miner can utilize characterized memories to generate memory hard proof-of-work (POW). The results may be further validated against general compute memories; such that only valid solutions are broadcasted to the mining community. In one embodiment, the validation mechanism is implemented for a plurality of searching apparatus in parallel to provide a more distributed and efficient approach. Various other applications for characterized memories are also described in greater detail herein (e.g., blockchain, social media, machine learning, probabilistic applications and other error-tolerant applications).

公开(公告)号：US11251096B2

公开(公告)日：2022-02-15

申请号：US16122106

申请日：2018-09-05

Applicant: Micron Technology, Inc.

Inventor： Nikolay A. Mirin ,  Robert Dembi ,  Richard T. Housley ,  Xiaosong Zhang ,  Jonathan D. Harms ,  Stephen J. Kramer

IPC: G03F7/20 ,  H01L21/68 ,  H01L21/66 ,  H01L23/544 ,  H01L21/302

Abstract: A method for measuring overlay between an interest level and a reference level of a wafer includes applying a magnetic field to a wafer, detecting at least one residual magnetic field emitted from at least one registration marker of a first set of registration markers within the wafer, responsive to the detected one or more residual magnetic fields, determining a location of the at least one registration marker of the first set registration markers, determining a location of at least one registration marker of a second set of registration markers, and responsive to the respective determined locations of the at least one registration marker of the first set of registration markers and the at least one registration marker of the second set of registration markers, calculating a positional offset between an interest level of the wafer and a reference level of the wafer. Related methods and systems are also disclosed.

公开(公告)号：US11217303B2

公开(公告)日：2022-01-04

申请号：US16581005

申请日：2019-09-24

Applicant: Micron Technology, Inc.

Inventor： Jonathan J. Strand ,  Sukneet Singh Basuta ,  Shashank Bangalore Lakshman ,  Jonathan D. Harms

IPC: G11C11/56 ,  G11C29/50 ,  G11C16/10 ,  G11C16/26 ,  G11C16/34 ,  G11C16/08

Abstract: Methods, systems, and devices for imprint recovery for memory arrays are described. In some cases, memory cells may become imprinted, which may refer to conditions where a cell becomes predisposed toward storing one logic state over another, resistant to being written to a different logic state, or both. Imprinted memory cells may be recovered using a recovery or repair process that may be initiated according to various conditions, detections, or inferences. In some examples, a system may be configured to perform imprint recovery operations that are scaled or selected according to a characterized severity of imprint, an operational mode, environmental conditions, and other factors. Imprint management techniques may increase the robustness, accuracy, or efficiency with which a memory system, or components thereof, can operate in the presence of conditions associated with memory cell imprinting.

公开(公告)号：US20210319843A1

公开(公告)日：2021-10-14

申请号：US17241893

申请日：2021-04-27

Applicant: Micron Technology, Inc.

Inventor： Jonathan D. Harms ,  Jonathan J. Strand ,  Sukneet Singh Basuta ,  Shashank Bangalore Lakshman

IPC: G11C29/50 ,  G11C11/22

Abstract: Methods, systems, and devices for imprint recovery for memory cells are described. In some cases, memory cells may become imprinted, which may refer to conditions where a cell becomes predisposed toward storing one logic state over another, resistant to being written to a different logic state, or both. Imprinted memory cells may be recovered using a recovery or repair process that may be initiated according to various conditions, detections, or inferences. In some examples, a system may be configured to perform imprint recovery operations that are scaled or selected according to a characterized severity of imprint, an operational mode, environmental conditions, and other factors. Imprint management techniques may increase the robustness, accuracy, or efficiency with which a memory system, or components thereof, can operate in the presence of conditions associated with memory cell imprinting.

公开(公告)号：US20210201195A1

公开(公告)日：2021-07-01

申请号：US16854107

申请日：2020-04-21

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Dmitry Vengertsev ,  Zahra Hosseinimakarem ,  Jonathan D. Harms

IPC: G06N20/00 ,  G06K9/62 ,  G06N3/04

Abstract: Data may be abstracted and/or masked prior to being provided to a machine learning model for training. A machine learning model may provide a confidence level associated with a result. If the confidence level is too high, the machine learning model or an application including the machine learning model may refrain from providing the result as an output. In some examples, the machine learning model may provide a “second best” result that has an acceptable confidence level. In other examples, an error signal may be provided as the output. In accordance with examples of the present disclosure, data may be abstracted and/or masked prior to being provided to a machine learning model for training and confidence levels of results of the trained machine learning model may be used to determine when a result should be withheld.

公开(公告)号：US10998080B2

公开(公告)日：2021-05-04

申请号：US16580972

申请日：2019-09-24

Applicant: Micron Technology, Inc.

Inventor： Jonathan D. Harms ,  Jonathan J. Strand ,  Sukneet Singh Basuta ,  Shashank Bangalore Lakshman

IPC: G11C11/22 ,  G11C29/50

Abstract: Methods, systems, and devices for imprint recovery for memory cells are described. In some cases, memory cells may become imprinted, which may refer to conditions where a cell becomes predisposed toward storing one logic state over another, resistant to being written to a different logic state, or both. Imprinted memory cells may be recovered using a recovery or repair process that may be initiated according to various conditions, detections, or inferences. In some examples, a system may be configured to perform imprint recovery operations that are scaled or selected according to a characterized severity of imprint, an operational mode, environmental conditions, and other factors. Imprint management techniques may increase the robustness, accuracy, or efficiency with which a memory system, or components thereof, can operate in the presence of conditions associated with memory cell imprinting.

公开(公告)号：US20210090680A1

公开(公告)日：2021-03-25

申请号：US16580935

申请日：2019-09-24

Applicant: Micron Technology, Inc.

Inventor： Shashank Bangalore Lakshman ,  Jonathan D. Harms ,  Jonathan J. Strand ,  Sukneet Singh Basuta

IPC: G11C29/50 ,  G11C11/56 ,  G11C16/10 ,  G11C16/08 ,  G11C16/26 ,  G11C16/34

Abstract: Methods, systems, and devices for imprint recovery management for memory systems are described. In some cases, memory cells may become imprinted, which may refer to conditions where a cell becomes predisposed toward storing one logic state over another, resistant to being written to a different logic state, or both. Imprinted memory cells may be recovered using a recovery or repair process that may be initiated according to various conditions, detections, or inferences. In some examples, a system may be configured to perform imprint recovery operations that are scaled or selected according to a characterized severity of imprint, an operational mode, environmental conditions, and other factors. Imprint management techniques may increase the robustness, accuracy, or efficiency with which a memory system, or components thereof, can operate in the presence of conditions associated with memory cell imprinting.