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    SOC for operating plural NPUS according to plural clock signals having multi-phases
    5.
    发明授权
    SOC for operating plural NPUS according to plural clock signals having multi-phases 有权

    公开(公告)号：US12117866B2

    公开(公告)日：2024-10-15

    申请号：US18473746

    申请日：2023-09-25

    申请人： DEEPX CO., LTD.

    发明人： Lok Won Kim ,  Jin Gun Song ,  Seong Jin Lee

    IPC分类号： G06F1/08 ,  G06F15/80

    CPC分类号： G06F1/08 ,  G06F15/80

    摘要： A system-on-chip (SoC) may comprise a semi-conductor substrate; a first circuitry, disposed on the semi-conductor substrate, provided for a first neural processing unit (NPU) configured to perform operations of an artificial neural network model (ANN); a second circuitry, disposed on the semi-conductor substrate, provided for a second NPU configured to perform operations of an ANN model, each of the first NPU and the second NPU including a plurality of processing elements (PEs), the plurality of PEs including an adder, a multiplier, and an accumulator; and a clock signal supply circuit, disposed on the semi-conductor substrate, configured to output one or more clock signals, wherein a first clock signal among the one or more clock signals may be supplied to the first NPU, and a second clock signal among the one or more clock signals may be supplied to the second NPU.

    LOW POWER AND AREA CLOCK MONITORING CIRCUIT USING A CAPACITOR AND CONSTANT CURRENT SINK
    6.
    发明公开
    LOW POWER AND AREA CLOCK MONITORING CIRCUIT USING A CAPACITOR AND CONSTANT CURRENT SINK 审中-公开

    公开(公告)号：US20240338051A1

    公开(公告)日：2024-10-10

    申请号：US18295560

    申请日：2023-04-04

    申请人： NIVIDIA Corporation

    发明人： Kedar Rajpathak ,  Tezaswi Raja

    IPC分类号： G06F1/08 ,  G06F1/12

    CPC分类号： G06F1/08 ,  G06F1/12

    摘要： Circuitry and a method of operating a clock monitoring circuit for monitoring a clock signal is disclosed. The method comprises charging a first capacitor connected to a connection between a first pair of transistors and a voltage reference, charging a second capacitor connected to a connection between a second pair of transistors and to the voltage reference, sinking a current from the first and second pair of transistors with a constant current sink, and asserting a clock slow detect (CSD) signal when a voltage at the constant current sink drops below a threshold indicating durations of phases of the clock signal lengthen.

    CONSUMER DEVICE FIRMWARE UPDATING VIA HDMI
    7.
    发明公开
    CONSUMER DEVICE FIRMWARE UPDATING VIA HDMI 审中-公开

    公开(公告)号：US20240329975A1

    公开(公告)日：2024-10-03

    申请号：US18740756

    申请日：2024-06-12

    申请人： Vizio, Inc.

    发明人： W. Leo Hoarty

    IPC分类号： G06F8/65 ,  G06F1/08 ,  G06F1/12

    CPC分类号： G06F8/65 ,  G06F1/08 ,  G06F1/12

    摘要： Systems and methods for updating firmware in an audio device, such as a soundbar, operatively connected to a Smart TV, are shown and described. Firmware update data is transmitted to the audio device via an audio return channel (ARC) of an HDMI cable. In certain of the systems, the firmware update data is transmitted to the audio device when no audio is being transmitted to or played by the audio device. In other systems, the firmware update data and real-time audio data are multiplexed by the Smart TV and are sent to the audio device via the audio return channel for subsequent demultiplexing and playback of the audio.

    Digital PDM microphone interface
    9.
    发明授权
    Digital PDM microphone interface 有权

    公开(公告)号：US12101611B2

    公开(公告)日：2024-09-24

    申请号：US17874210

    申请日：2022-07-26

    申请人： SYNTIANT

    发明人： Joseph Cordaro ,  David Garrett

    IPC分类号： H04R3/00 ,  G06F1/08 ,  G06F1/12 ,  H04R19/04 ,  H03K3/037

    CPC分类号： H04R3/005 ,  G06F1/08 ,  G06F1/12 ,  H04R19/04 ,  H03K3/037 ,  H04R2201/003

    摘要： A clocking technique for reducing the power of PDM microphones in dual microphone systems is disclosed. A clock for a conventional PDM microphone (PDMCLK) is provided by another source. PDM microphones send serial data (PDMDAT) on the rising (“Right”) or falling (“Left”) edge of the PDMCLK clock, depending on how the microphone is configured. In a dual PDM microphone configuration, the microphones alternate sending data on the rising edges (transitions to logic-1) and falling edges (transitions to logic-0) of PDMCLK. Typically, Complementary Metal-Oxide-Semiconductor (CMOS) logic is used to transmit or drive the clock signal to the microphones. CMOS drivers consume power primarily when they transition from a logic-0 to a logic-1 or from a logic-1 to a logic-0. Thus, a free-running clock signal will produce the highest CMOS power consumption. In a dual PDM microphone system, it is desirable to operate in a low power mode with a single microphone at times and to operate with the full functionality (and power consumption) of both microphones at other times. In a conventional system, both PDM microphones share both the PDMDAT and PDMCLK signal lines. Thus both microphones must be clocked even if only one is being used. This wastes power in both the PDMCLK output buffer (driving both loads even if one is not being used) as well as in the unused microphone (where all of the clock circuits are active and switching). A novel PDM microphone interface is disclosed that provides a three signal interface comprising a separate PDMCLK signal to each microphone while maintaining a single common PDMDAT line.