公开(公告)号：US20250068208A1

公开(公告)日：2025-02-27

申请号：US18454973

申请日：2023-08-24

Applicant: Realtek Semiconductor Corp.

Inventor： Chia-Liang (Leon) Lin

IPC: G06F1/08 ,  G06F1/10

Abstract: A clock transmission circuit includes a voltage-to-current converter configured to convert a first clock into a first current; a transmission line configured to convey the first current into a second current; a transformer comprising a primary inductor and a secondary inductor and configured to convert the second current received via the primary inductor into a second clock output via the secondary inductor; a tuning capacitor configured to form a resonance with the secondary inductor; and a regenerative network connected to the secondary inductor and configured to provide a negative resistance to reinforce the resonance.

公开(公告)号：US12235675B2

公开(公告)日：2025-02-25

申请号：US18637461

申请日：2024-04-17

Applicant: Samsung Display Co., Ltd.

Inventor： Se-Byung Chae

IPC: G06F1/12 ,  G06F1/08 ,  G09G3/32 ,  G09G3/3225

Abstract: A signal generator may include a reference horizontal synchronization signal generation block which generates reference horizontal synchronization signals based on a number of clock signals per a horizontal time, a frame clock calculation block which calculates a first frame clock number based on a number of the clock signals per the horizontal time, a frame clock comparation block which calculates a clock offset by comparing the first frame clock number and a second frame clock number generated based on a number of the clock signals per a frame time, a clock distribution block which generates horizontal synchronization signals by distributing a number of the clock signals corresponding to the clock offset to the reference horizontal synchronization signals, and a vertical synchronization signal generation block which generates a vertical synchronization signal based on the horizontal synchronization signals.

公开(公告)号：US12231126B1

公开(公告)日：2025-02-18

申请号：US18127771

申请日：2023-03-29

Applicant: Keysight Technologies, Inc.

Inventor： Nathaniel Guilar ,  John Patrick Keane ,  Robert Neff

IPC: H03K5/01 ,  G06F1/08 ,  H03L7/081 ,  H03K5/00

Abstract: A device for generating a sampling strobe, which controls a sampling device to sample an input signal, includes a phase shifter configured to phase shift an input clock to provide multiple phase shifted input clock signals; and aperture generating circuits configured to generate sampling clock signals from the phase shifted input clock signals, respectively, by adjusting duty cycles of the phase shifted input clock signals to provide sampling pulses having desired pulse widths, where for each sampling clock signal of the sampling clock signals, a rising edge and a falling edge of each sampling pulse originate from the same input edge of the input clock; and apply the sampling clock signals to interleaved samplers of the sampling device, respectively, for controlling sampling of the input signal by integrating according to the desired pulse widths of the sampling pulses, where the desired pulse widths correspond to sampling apertures.

公开(公告)号：US12228962B1

公开(公告)日：2025-02-18

申请号：US18227255

申请日：2023-07-27

Applicant: Diodes Incorporated

Inventor： Yu-Wei Lin

IPC: G06F1/10 ,  G06F1/08

Abstract: An apparatus includes a clock skew calibration circuit configured to be coupled to a multi-phase clock generator through a plurality of delay lines, wherein a first clock skew calibration unit comprises a frequency doubler configured to receive a plurality of multi-phase clock signals and generate a clock signal based on the plurality of multi-phase clock signals, a frequency divider configured to receive the clock signal and generate a reduced frequency signal based on the clock signal, and a delay line control circuit configured to compare the duty cycle of the reduced frequency signal with a predetermined duty cycle, and generate a first control signal to adjust the skew of the first multi-phase clock signal through adjusting a first delay applied to the first multi-phase clock signal until a calibrated signal of the first multi-phase clock signal is achieved.

公开(公告)号：US20250053524A1

公开(公告)日：2025-02-13

申请号：US18807548

申请日：2024-08-16

Applicant: Rambus Inc.

Inventor： Jared L. Zerbe ,  Ian P. Shaeffer ,  John Eble

IPC: G06F13/16 ,  G06F1/04 ,  G06F1/06 ,  G06F1/08 ,  G06F1/10 ,  G11C7/04 ,  G11C7/22 ,  H04L7/033

Abstract: A memory controller includes a clock generator to generate a first clock signal and a timing circuit to generate a second clock signal from the first clock signal. The second clock signal times communications with any of a plurality of memory devices in respective ranks, including a first memory device in a first rank and a second memory device in a second rank. The timing circuit is configured to adjust a phase of the first clock signal, when the memory controller is communicating with the second memory device, based on calibration data associated with the second memory device and timing adjustment data associated with feedback from at least the first memory device.

公开(公告)号：US20250053188A1

公开(公告)日：2025-02-13

申请号：US18231133

申请日：2023-08-07

Applicant: InnoGrit Technologies Co., Ltd.

Inventor： Gang Zhao ,  Jie Chen ,  Abhilash Matthew ,  Wei Jiang ,  Lin Chen

IPC: G06F1/08

Abstract: Disclosed herein is a new technique for providing a storage controller with variable interface communication speeds to allow the storage controller to set different communication speeds and frequencies for different communication channels between the storage controller and respective memories. A controller comprises: a processor; registers; and a clock generator configured to generate clock signals respectively for multiple communication channels based on values stored in the registers. The controller is configured to communicate with non-volatile memories through the communication channels respectively using the clock signals.

公开(公告)号：US20250044825A1

公开(公告)日：2025-02-06

申请号：US18365006

申请日：2023-08-03

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Sandeep Goel ,  Ankita Patidar ,  YUN-HAN LEE

IPC: G06F1/08

Abstract: A semiconductor device includes an on-chip clock controller configured to provide a clock output signal and configured to receive a mode signal and a speed enable signal, and to generate a first fast clock enable signal and a first slow clock enable signal. The on-chip clock controller is configured to override the first fast clock enable signal based on the mode signal and the speed enable signal to provide a fast clock in the clock output signal and to override the first slow clock enable signal based on the mode signal and the speed enable signal to provide a slow clock in the clock output signal.

公开(公告)号：US20250028352A1

公开(公告)日：2025-01-23

申请号：US18904770

申请日：2024-10-02

Applicant: pSemi Corporation

Inventor： Gerald ALCORN

IPC: G06F1/08 ,  G05B19/045 ,  H03K19/17704

Abstract: Methods and apparatuses for an optimal timer array using a single reference counter are presented. According to one aspect, timers of the timer array use the single reference counter to process different timed trigger requests. A count translation logic block translates counts corresponding to the requested timed triggers to target values of the reference counter. Register arrays that include the target values and active/inactive status flags of the timers are used to implement specific timers. Comparators are used to compare values of the reference counter to the target values to establish expiration of the requested timed triggers. A target translation logic block translates a current value of the reference counter to an offset value from the target values for monitoring by an external circuit.

公开(公告)号：US12204792B2

公开(公告)日：2025-01-21

申请号：US17396117

申请日：2021-08-06

Applicant: Micron Technology, Inc.

Inventor： Reshmi Basu ,  David Aaron Palmer ,  Jonathan S. Parry

IPC: G06F3/06 ,  G06F1/08

Abstract: Methods, systems, and devices for adaptive throughput monitoring are described. In some examples, a memory system may be associated with one or more clocks that are each associated with a respective subcomponent. When the memory system receives a plurality of commands, the memory system may determine a throughput of the commands. Based on the determined throughput, the memory system may adjust a rate of one or more of the clocks.

公开(公告)号：US12204366B2

公开(公告)日：2025-01-21

申请号：US18314656

申请日：2023-05-09

Applicant: SK hynix Inc.

Inventor： Ji Hyo Kang ,  Kyung Hoon Kim

IPC: G06F1/10 ,  G06F1/08 ,  H03K19/0185

Abstract: A clock distribution network includes a global clock tree and a local clock tree. When the clock distribution network is activated, the local clock tree is first activated, and the voltage levels of first and second output clock signals are set as a common mode voltage level. When the global clock tree is activated, the global clock tree generates first and second global clock signals from first and second input clock signals. The local clock tree generates the first and second output clock signals from the first and second global clock signals.