公开(公告)号：US20240363189A1

公开(公告)日：2024-10-31

申请号：US18471307

申请日：2023-09-21

申请人： SK hynix Inc.

发明人： Young Ook SONG

IPC分类号： G11C29/52 ,  G11C7/10 ,  G11C7/20 ,  G11C7/22

CPC分类号： G11C29/52 ,  G11C7/1069 ,  G11C7/20 ,  G11C7/222

摘要： A memory system includes a plurality of memory devices; and a memory controller configured to perform an initial training operation to set a plurality of time codes corresponding to the plurality of memory devices, respectively, receive a plurality of data signals read from the plurality of memory devices, as internal data signals, according to the plurality of time codes, respectively, and adjust the plurality of time codes based on the internal data signals and error pattern maps generated by collecting error location information for the internal data signals.

公开(公告)号：US12125558B2

公开(公告)日：2024-10-22

申请号：US18310302

申请日：2023-05-01

申请人： MICRON TECHNOLOGY, INC.

发明人： Kang-Yong Kim

IPC分类号： G11C7/22 ,  G11C7/10 ,  G11C11/4076 ,  H03K5/156

CPC分类号： G11C7/222 ,  G11C7/1063 ,  G11C7/109 ,  G11C7/225 ,  G11C11/4076 ,  H03K5/1565

摘要： Apparatuses and methods for setting a duty cycler adjuster for improving clock duty cycle are disclosed. The duty cycle adjuster may be adjusted by different amounts, at least one smaller than another. Determining when to use the smaller adjustment may be based on duty cycle results. A duty cycle monitor may have an offset. A duty cycle code for the duty cycle adjuster may be set to an intermediate value of a duty cycle monitor offset. The duty cycle monitor offset may be determined by identifying duty cycle codes for an upper and for a lower boundary of the duty cycle monitor offset.

公开(公告)号：US12125557B2

公开(公告)日：2024-10-22

申请号：US18164570

申请日：2023-02-04

申请人： NANYA TECHNOLOGY CORPORATION

发明人： Shun-Ke Wu

IPC分类号： G11C11/4093 ,  G11C7/10 ,  G11C7/22

CPC分类号： G11C7/222 ,  G11C7/1093 ,  G11C7/1096

摘要： An electronic device, a memory device of the electronic device, and a write leveling method of the memory device are provided. The memory device is coupled to a memory controller to receive a data strobe signal DQS and a clock signal CLK. In a write leveling mode, the memory device provides a write leveling function to the memory controller, where the write leveling function includes a plurality of iterative operations. In each of the iterative operations, the memory controller sends a notification to the memory device, and the memory device sets up a strobe window based on the notification. The memory device samples the clock signal CLK based on a phase of the data strobe signal DQS in the strobe window, so as to send a sampling result back to the memory controller. The memory device is prohibited from sampling the clock signal CLK outside the strobe window.

公开(公告)号：US20240347099A1

公开(公告)日：2024-10-17

申请号：US18301769

申请日：2023-04-17

申请人： QUALCOMM Incorporated

发明人： Joon Young PARK

IPC分类号： G11C11/4076 ,  G11C7/22

CPC分类号： G11C11/4076 ,  G11C7/22

摘要： A signal driving circuit includes a first transmitting circuit having an input coupled to a source of a chip select signal and an output that is configured to switch within a first voltage range having a first amplitude, a second transmitting circuit having an input coupled to the source of the chip select signal and an output that is configured to switch within a second voltage range having a second amplitude, and an output node coupled to the output of the first transmitting circuit and the output of the second transmitting circuit. The first amplitude may be lower than the second amplitude.

公开(公告)号：US20240347087A1

公开(公告)日：2024-10-17

申请号：US18754823

申请日：2024-06-26

申请人： KIOXIA CORPORATION

发明人： Zhao LU ,  Yuji NAGAI ,  Akio SUGAHARA ,  Takehisa KUROSAWA ,  Masaru KOYANAGI

IPC分类号： G11C7/22 ,  G11C7/08 ,  G11C7/10

CPC分类号： G11C7/222 ,  G11C7/08 ,  G11C7/1063 ,  G11C7/109

摘要： A semiconductor memory device includes: first pad transmitting and receiving first timing signal; second pad transmitting and receiving data signal in response to the first timing signal; third pad receiving second timing signal; fourth pad receiving control information in response to the second timing signal; memory cell array; sense amplifier connected to the memory cell array; first register connected to the sense amplifier; second register storing first control information; third register storing second control information; and control circuit executing data-out operation. The first control information is stored in the second register based on an input to the fourth pad in response to the second timing signal consisting of i cycles, and the second control information is stored in the third register based on an input to the fourth pad in response to the second timing signal consisting of j cycles.

公开(公告)号：US20240347086A1

公开(公告)日：2024-10-17

申请号：US18458165

申请日：2023-08-30

申请人： SK hynix Inc.

发明人： Chan Keun KWON ,  Se Jin KANG ,  In Seok KONG

IPC分类号： G11C7/22 ,  G11C7/10

CPC分类号： G11C7/222 ,  G11C7/1066 ,  G11C7/1069 ,  G11C7/1096

摘要： A signal transmission circuit comprising: a first data transmission circuit configured to output, through a first data output node thereof and in response to a first operation clock applied to a first clock input node thereof, first output data obtained by sensing and amplifying a first input data pair applied to a first differential input node pair thereof, a clock transmission circuit configured to output through a second data output node thereof, a second operation clock generated in response to the first operation clock applied to a second clock input node thereof while a power supply voltage and a ground voltage are applied to a second differential input node pair thereof, and a first data output circuit configured to output the first output data in synchronization with the second operation clock, wherein the first data transmission circuit is modeled on the clock transmission circuit.

公开(公告)号：US20240347085A1

公开(公告)日：2024-10-17

申请号：US18473837

申请日：2023-09-25

申请人： Samsung Electronics Co., Ltd.

发明人： Dongin SEO ,  Jaewoong KIM ,  Changhyun BAE ,  Hyeseung YU

IPC分类号： G11C7/20 ,  G11C7/10 ,  G11C7/22

CPC分类号： G11C7/20 ,  G11C7/106 ,  G11C7/1063 ,  G11C7/222

摘要： A receiver includes a buffer configured to generate an internal data signal by comparing a received data signal with a reference voltage, a decision feedback equalizer configured to generate a sampled signal based on a present value of the internal data signal and on a feedback signal, and configured to provide one of the sampled signal or a first logic level as the feedback signal based on a reset control signal, the sampled signal corresponding to a previous value of the internal data signal, a deserializer configured to generate an output data by deserializing the sampled signal, and a reset control circuit configured to generate the reset control signal based on operating information associated with a write operation of the data signal and configured to provide the reset control signal to the decision feedback equalizer.

公开(公告)号：US20240345971A1

公开(公告)日：2024-10-17

申请号：US18629167

申请日：2024-04-08

申请人： Rambus Inc.

发明人： Frederick A. Ware ,  Amir Amirkhany ,  Suresh Rajan ,  Mohammad Hekmat ,  Dinesh Patil

IPC分类号： G06F13/16 ,  G06F13/40 ,  G11C5/02 ,  G11C7/10 ,  G11C7/22 ,  G11C8/18 ,  G11C11/4076 ,  G11C11/4093 ,  G11C11/4096 ,  G11C11/419 ,  G11C29/02

CPC分类号： G06F13/1673 ,  G06F13/4068 ,  G11C5/02 ,  G11C7/10 ,  G11C7/1012 ,  G11C7/1021 ,  G11C7/106 ,  G11C7/1066 ,  G11C7/1072 ,  G11C7/1087 ,  G11C7/1093 ,  G11C7/222 ,  G11C8/18 ,  G11C11/4076 ,  G11C11/4093 ,  G11C11/4096 ,  G11C11/419 ,  G11C29/022 ,  G11C29/023 ,  G11C29/028

摘要： A semiconductor memory system includes a first semiconductor memory die and a second semiconductor memory die. The first semiconductor memory die includes a primary data interface to receive an input data stream during write operations and to deserialize the input data stream into a first plurality of data streams, and also includes a secondary data interface, coupled to the primary data interface, to transmit the first plurality of data streams. The second semiconductor memory die includes a secondary data interface, coupled to the secondary data interface of the first semiconductor memory die, to receive the first plurality of data streams.

公开(公告)号：US20240345618A1

公开(公告)日：2024-10-17

申请号：US18629138

申请日：2024-04-08

申请人： Rambus Inc.

发明人： Frederick A. Ware

IPC分类号： G06F1/08 ,  G06F1/04 ,  G06F1/06 ,  G06F1/10 ,  G06F1/12 ,  G11C7/02 ,  G11C7/04 ,  G11C7/10 ,  G11C7/22

CPC分类号： G06F1/08 ,  G06F1/04 ,  G11C7/02 ,  G11C7/04 ,  G11C7/1066 ,  G11C7/1093 ,  G11C7/222 ,  G06F1/06 ,  G06F1/10 ,  G06F1/12

摘要： The disclosed embodiments relate to a memory system that generates a multiplied timing signal from a reference timing signal. During operation, the system receives a reference timing signal. Next, the system produces a multiplied timing signal from the reference timing signal by generating a burst comprising multiple timing events for each timing event in the reference timing signal, wherein consecutive timing events in each burst of timing events are separated by a bit time. Then, as the reference clock frequency changes, the interval between bursts of timing events changes while the bit time remains substantially constant.

公开(公告)号：US20240339139A1

公开(公告)日：2024-10-10

申请号：US18746238

申请日：2024-06-18

申请人： Kioxia Corporation

发明人： Hiroki DATE

IPC分类号： G11C7/22 ,  G11C16/08 ,  G11C16/10 ,  G11C16/28 ,  G11C16/32 ,  H10B41/27 ,  H10B41/35 ,  H10B41/40 ,  H10B43/27 ,  H10B43/35 ,  H10B43/40

CPC分类号： G11C7/22 ,  G11C16/08 ,  G11C16/10 ,  G11C16/28 ,  G11C16/32 ,  H10B43/27 ,  H10B43/35 ,  H10B43/40 ,  H10B41/27 ,  H10B41/35 ,  H10B41/40

摘要： In a semiconductor memory device, in a write operation performed to a memory cell transistor, a first voltage is applied to a first word line and a second voltage lower than the first voltage is applied to a second word line. When a stop command is received during the write operation, a third voltage lower than the second voltage is applied to the first and second word lines, thereafter a fourth voltage higher than the third voltage is applied to a first selection line, thereon or thereafter a fifth voltage higher than the fourth voltage is applied to the first and second word lines, thereafter a sixth voltage lower than the fourth voltage is applied to the first selection line, and thereafter a seventh voltage is applied to the first and second word lines.