公开(公告)号：US20240313527A1

公开(公告)日：2024-09-19

申请号：US18584301

申请日：2024-02-22

申请人： Kioxia Corporation

发明人： Shigefumi ISHIGURO ,  Yasuhiro SUEMATSU ,  Masaru KOYANAGI ,  Maya INAGAKI ,  Kentaro WATANABE ,  Shoki ITO

IPC分类号： H02H9/04

CPC分类号： H02H9/046

摘要： A semiconductor device includes a protection circuit electrically connected to a first interconnection and a second interconnection, a first voltage and a second voltage supplied to the first interconnection and the second interconnection, respectively. The protection circuit includes: a first resistor connected between the first interconnection and a first node; a first capacitor connected between the second interconnection and the first node; a second resistor connected between the second interconnection and a second node located; a second capacitor connected between the second interconnection and the second node, and connected in parallel to the second resistor; a third resistor connected between the first interconnection and a third node; and a third capacitor connected between the second interconnection and the third node.

公开(公告)号：US20230223938A1

公开(公告)日：2023-07-13

申请号：US18125081

申请日：2023-03-22

申请人： Kioxia Corporation

发明人： Junya MATSUNO ,  Kensuke YAMAMOTO ,  Ryo FUKUDA ,  Masaru KOYANAGI ,  Kenro KUBOTA ,  Masato DOME

IPC分类号： G11C7/10

CPC分类号： G11C7/1048

摘要： A device includes a memory cell array configured to store data; and a signal propagation circuit configured to propagate a signal between the memory cell array and a host. The signal propagation circuit includes a first inverted signal output circuit, a second inverted signal output circuit including an input terminal connected to i) an output terminal of the first inverted signal output circuit and ii) an output terminal of the second inverted signal output circuit, a third inverted signal output circuit including an input terminal connected to i) the output terminal of the first inverted signal output circuit and ii) the output terminal of the second inverted signal output circuit, and a fourth inverted signal output circuit including an input terminal connected to i) an output terminal of the third inverted signal output circuit and ii) an output terminal of the fourth inverted signal output circuit.

公开(公告)号：US20210409023A1

公开(公告)日：2021-12-30

申请号：US17473012

申请日：2021-09-13

申请人： KIOXIA CORPORATION

发明人： Yasuhiro HIRASHIMA ,  Masaru KOYANAGI ,  Yutaka TAKAYAMA

IPC分类号： H03K19/0175 ,  H01L23/538

摘要： A semiconductor device includes a latch circuit including a first inverter configured to output a first signal based on an input signal, a second inverter configured to output a first clock signal based on a first strobe signal, a third inverter configured to output a second clock signal based on a second strobe signal, a first clock generation circuit configured to generate a third clock signal having transitions that are delayed with respect to the first clock signal, a second clock generation circuit configured to generate a fourth clock signal having transitions that are delayed with respect to the second clock signal, a fourth inverter configured to output an inversion signal of the first signal in accordance with the third and fourth clock signals, and a data latch circuit configured to latch an output signal of the fourth inverter.

公开(公告)号：US20240347087A1

公开(公告)日：2024-10-17

申请号：US18754823

申请日：2024-06-26

申请人： KIOXIA CORPORATION

发明人： Zhao LU ,  Yuji NAGAI ,  Akio SUGAHARA ,  Takehisa KUROSAWA ,  Masaru KOYANAGI

IPC分类号： G11C7/22 ,  G11C7/08 ,  G11C7/10

CPC分类号： G11C7/222 ,  G11C7/08 ,  G11C7/1063 ,  G11C7/109

摘要： A semiconductor memory device includes: first pad transmitting and receiving first timing signal; second pad transmitting and receiving data signal in response to the first timing signal; third pad receiving second timing signal; fourth pad receiving control information in response to the second timing signal; memory cell array; sense amplifier connected to the memory cell array; first register connected to the sense amplifier; second register storing first control information; third register storing second control information; and control circuit executing data-out operation. The first control information is stored in the second register based on an input to the fourth pad in response to the second timing signal consisting of i cycles, and the second control information is stored in the third register based on an input to the fourth pad in response to the second timing signal consisting of j cycles.

公开(公告)号：US20230188137A1

公开(公告)日：2023-06-15

申请号：US18165195

申请日：2023-02-06

申请人： Kioxia Corporation

发明人： Yasuhiro HIRASHIMA ,  Masaru KOYANAGI ,  Yutaka TAKAYAMA

IPC分类号： H03K19/0175 ,  H01L23/538

CPC分类号： H03K19/017509 ,  H01L23/5384

摘要： A semiconductor device includes a latch circuit including a first inverter configured to output a first signal based on an input signal, a second inverter configured to output a first clock signal based on a first strobe signal, a third inverter configured to output a second clock signal based on a second strobe signal, a first clock generation circuit configured to generate a third clock signal having transitions that are delayed with respect to the first clock signal, a second clock generation circuit configured to generate a fourth clock signal having transitions that are delayed with respect to the second clock signal, a fourth inverter configured to output an inversion signal of the first signal in accordance with the third and fourth clock signals, and a data latch circuit configured to latch an output signal of the fourth inverter.

公开(公告)号：US20230018613A1

公开(公告)日：2023-01-19

申请号：US17952659

申请日：2022-09-26

申请人： Kioxia Corporation

发明人： Junya MATSUNO ,  Kenro KUBOTA ,  Masato DOME ,  Kensuke YAMAMOTO ,  Kei SHIRAISHI ,  Kazuhiko SATOU ,  Ryo FUKUDA ,  Masaru KOYANAGI

IPC分类号： G11C16/32 ,  G11C16/04

摘要： A semiconductor device includes a first circuit configured to receive a first signal, and output a first voltage to a first node in accordance with a voltage of the first signal being at a first level and output a second voltage to the first node in accordance with the voltage of the first signal being at a second level, the first voltage being higher than the second voltage. A second circuit is coupled to the first node and is configured to latch data based on a voltage of the first node; and a third circuit is coupled to the first node and is configured to output a third voltage to the first node while the first circuit is outputting the first voltage to the first node, and to output a fourth voltage to the first node while the first circuit is outputting the second voltage to the first node, the third voltage being lower than the first voltage, and the fourth voltage being higher than the second voltage.

公开(公告)号：US20220158639A1

公开(公告)日：2022-05-19

申请号：US17588702

申请日：2022-01-31

申请人： Kioxia Corporation

发明人： Junya MATSUNO ,  Kensuke YAMAMOTO ,  Ryo FUKUDA ,  Masaru KOYANAGI ,  Kenro KUBOTA ,  Masato DOME

IPC分类号： H03K19/0185 ,  G11C7/10

摘要： A semiconductor memory device includes a memory cell array and a signal propagation circuit disposed on a propagation path of a signal or a control signal. The signal propagation circuit includes a first inverted signal output circuit; a second inverted signal output circuit including an input terminal connected to an output terminal of the first inverted signal output circuit; a third inverted signal output circuit including an input terminal connected to output terminals of the first inverted signal output circuit and the second inverted signal output circuit; a fourth inverted signal output circuit including an input terminal connected to an output terminal of the third inverted signal output circuit, and further including a terminal connected to output terminals of the third inverted signal output circuit and the fourth inverted signal output circuit.

公开(公告)号：US20240312532A1

公开(公告)日：2024-09-19

申请号：US18672202

申请日：2024-05-23

申请人： Kioxia Corporation

发明人： Junya MATSUNO ,  Kenro KUBOTA ,  Masato DOME ,  Kensuke YAMAMOTO ,  Kei SHIRAISHI ,  Kazuhiko SATOU ,  Ryo FUKUDA ,  Masaru KOYANAGI

IPC分类号： G11C16/32 ,  G11C16/04 ,  G11C16/08 ,  G11C16/26 ,  H10B69/00

CPC分类号： G11C16/32 ,  G11C16/0483 ,  G11C16/08 ,  G11C16/26 ,  H10B69/00

摘要： A semiconductor memory device includes a memory cell array having a memory cell; a data signal terminal configured to receive data to be written into the memory cell from an exterior of the semiconductor memory device and to output data read from the memory cell to the exterior of the semiconductor memory, and a timing signal terminal configured to receive a timing control signal. An interface circuit includes a first comparator having a first input terminal connected to the data signal terminal, a second input terminal connected to a reference voltage, and an output terminal. A plurality of first inverters are connected in series, an input terminal of a first stage one of the first inverters being connected to the output terminal first of the first comparator. A first switch circuit has a first terminal connected to an output terminal of a final stage one of the first inverters and a second terminal; a second inverter having an input terminal connected to the second terminal of the first switch and an output terminal connected to the second terminal of the first switch; and a first latch circuit connected to the second terminal of the first switch.

公开(公告)号：US20230028971A1

公开(公告)日：2023-01-26

申请号：US17959098

申请日：2022-10-03

申请人： Kioxia Corporation

发明人： Masato DOME ,  Kensuke YAMAMOTO ,  Masaru KOYANAGI ,  Ryo FUKUDA ,  Junya MATSUNO ,  Kenro KUBOTA

IPC分类号： G11C16/30 ,  G11C16/04

摘要： According to one embodiment, a semiconductor memory device includes: first and second circuit units, a driver circuit, an input/output pad, first and second power supply pads, and first and second interconnects. The first interconnect is configured to provide coupling between the first circuit unit and the first power supply pad. The second interconnect is configured to provide coupling between the second circuit unit and the first power supply pad and have no electrical coupling to the first interconnect.

公开(公告)号：US20230022082A1

公开(公告)日：2023-01-26

申请号：US17806965

申请日：2022-06-15

申请人： KIOXIA CORPORATION

发明人： Zhao LU ,  Yuji NAGAI ,  Akio SUGAHARA ,  Takehisa KUROSAWA ,  Masaru KOYANAGI

IPC分类号： G11C7/22 ,  G11C7/10 ,  G11C7/08

摘要： A semiconductor memory device includes: first pad transmitting and receiving first timing signal; second pad transmitting and receiving data signal in response to the first timing signal; third pad receiving second timing signal; fourth pad receiving control information in response to the second timing signal; memory cell array; sense amplifier connected to the memory cell array; first register connected to the sense amplifier; second register storing first control information; third register storing second control information; and control circuit executing data-out operation. The first control information is stored in the second register based on an input to the fourth pad in response to the second timing signal consisting of i cycles, and the second control information is stored in the third register based on an input to the fourth pad in response to the second timing signal consisting of j cycles.