公开(公告)号：US12237023B2

公开(公告)日：2025-02-25

申请号：US17134010

申请日：2020-12-24

Applicant: Intel NDTM US LLC

Inventor： Tarek Ahmed Ameen Beshari ,  Shantanu R. Rajwade ,  Matin Amani ,  Narayanan Ramanan

IPC: G11C16/00 ,  G11C16/08 ,  G11C16/10 ,  G11C16/26 ,  G11C16/30 ,  G11C16/34

Abstract: For a nonvolatile (NV) storage media such as NAND media that is written by a program and program verify operation, the system can determine an expected number of SSPC (selective slow programming convergence) cells for a page of cells for specific conditions of the page. The system can perform program verify with a first wordline (WL) select voltage for SSPC cell detection for a first write of the page to detect the expected number of SSPC cells. Based on the determined expected number of SSPC cells, the system can set a boost voltage to capture an expected number of SSPC cells during the program verify operation. The system performs program verify for subsequent writes to the page with a higher WL select voltage, to perform program verify for standard cells and then SSPC program verify with the boost voltage determined from the first write.

公开(公告)号：US20250061953A1

公开(公告)日：2025-02-20

申请号：US18936629

申请日：2024-11-04

Applicant: Kioxia Corporation

Inventor： Tetsuaki UTSUMI

IPC: G11C16/30 ,  G11C16/08 ,  G11C16/24 ,  G11C16/26 ,  H10B41/10 ,  H10B41/35 ,  H10B41/41 ,  H10B43/10 ,  H10B43/35 ,  H10B43/40

Abstract: A semiconductor memory device includes word lines, first and second select gate lines, first and second semiconductor columns, first and second bit lines, and first and second transistors. The word lines are arranged in a first direction. The first and second select gate lines extend in a second direction and overlap with the word lines viewed from the first direction. The first and second select gate lines are arranged in the second direction. The first semiconductor column is opposed to the word lines and the first select gate line. The second semiconductor column is opposed to the word lines and the second select gate line. The first and second bit lines extend in a third direction and overlap with the first and second semiconductor columns viewed from the first direction. The first and second transistors are electrically connected to the first and second select gate lines.

公开(公告)号：US20250054554A1

公开(公告)日：2025-02-13

申请号：US18430892

申请日：2024-02-02

Applicant: SK hynix Inc.

Inventor： Won Jae CHOI ,  Chang Hee LEE ,  Hyun Chul CHO

IPC: G11C16/30 ,  G11C16/04 ,  G11C16/24

Abstract: According to an embodiment of the present disclosure, a memory device includes a memory cell array including a plurality of planes; a charge pump configured to generate an operating voltage used for an operation on each of the plurality of planes according to a first clock signal having a first cycle; page buffers each configured to store pass data representing whether an operation of each of the plurality of planes has been completed; and an operation control circuit configured to, based on a number of the pass data received from the page buffers, control the charge pump to generate the operating voltage according to a second clock signal having a second cycle that is longer than the first cycle.

公开(公告)号：US20250054552A1

公开(公告)日：2025-02-13

申请号：US18807792

申请日：2024-08-16

Applicant: STMicroelectronics International N.V.

Inventor： Vikas RANA ,  Neha DALAL

IPC: G11C16/26 ,  G11C16/04 ,  G11C16/08 ,  G11C16/30 ,  G11C16/32

Abstract: The present disclosure is directed to an integrated circuit that includes a non-volatile memory (NVM). The integrated circuit includes a bias generator that produces stable wordline and bitline voltages for a reliable read operation of the NVM. This disclosure is directed to low voltage memory operations of memory read, erase verify, and program verify. The present disclosure is directed to non-volatile memory circuits that can also operate at low supply voltages in digital voltage supply range.

公开(公告)号：US20250053222A1

公开(公告)日：2025-02-13

申请号：US18931954

申请日：2024-10-30

Applicant: Lodestar Licensing Group LLC

Inventor： Greg Blodgett ,  Daniele Balluchi ,  Danilo Caraccio ,  Graziano Mirichigni

IPC: G06F1/3234 ,  G06F1/30 ,  G06F1/3212 ,  G06F11/30 ,  G06F13/16 ,  G11C5/14 ,  G11C11/4072 ,  G11C11/4074 ,  G11C16/20 ,  G11C16/30

Abstract: The present disclosure includes apparatuses and methods for providing energy information to memory. An embodiment includes determining, by a host, that a charge level of an energy source coupled to the host has reached or exceeded a threshold value, and transmitting, from the host to a memory device coupled to the host, signaling indicative of an energy mode for the memory device, wherein the signaling is transmitted based at least in part on determining that the charge level of the energy source has reached or exceeded the threshold.

公开(公告)号：US12217808B2

公开(公告)日：2025-02-04

申请号：US17816720

申请日：2022-08-01

Applicant: NEO Semiconductor, Inc.

Inventor： Fu-Chang Hsu

IPC: G11C16/00 ,  G11C16/12 ,  G11C16/24 ,  G11C16/30 ,  G11C16/34

Abstract: Methods and apparatus for NAND flash memory are disclosed. In an embodiment, a method is provided for programming a memory device having a plurality of memory chips that comprise multiple-level-cells. The method includes loading first data in a first chip, programming the first data into selected cells of the first chip using a single-level-cell (SLC) programming mode, and reprogramming the first data stored in the selected cells of the first chip to other cells of the first chip using a multiple-level-cell programming mode. The method also includes repeating the operations of loading, programming, and reprogramming for the remaining chips. The loading operations for the remaining chips begin at the completion of the loading operation for the first chip and occur in a non-overlapping sequential manner, and the loading operations for the remaining chips are performed in parallel with the programming and reprogramming operations of the first chip.

公开(公告)号：US12217805B2

公开(公告)日：2025-02-04

申请号：US17903617

申请日：2022-09-06

Applicant: Kabushiki Kaisha Toshiba ,  Toshiba Electronic Devices & Storage Corporation

Inventor： Osamu Hirabayashi

IPC: G11C16/30 ,  G05F3/26 ,  G11C16/26 ,  G11C16/32

Abstract: A reference voltage generating circuit according to an embodiment includes: an original reference voltage generating unit that generates an original reference voltage; and a reference voltage correcting unit that decreases the original reference voltage as the temperature rises and outputs the original reference voltage as a reference voltage to a sense amplifier, and thus it is possible to perform highly reliable operation while the influence of the temperature is reduced.

公开(公告)号：US20250037775A1

公开(公告)日：2025-01-30

申请号：US18919022

申请日：2024-10-17

Applicant: Kioxia Corporation

Inventor： Takeshi HIOKA

IPC: G11C16/30 ,  G11C16/04 ,  G11C16/24 ,  G11C16/26

Abstract: A semiconductor memory device includes first and second memory cell transistors between first and second select transistors, third and fourth memory cell transistors between third and fourth select transistors, a first word line for first and third memory cell transistors, a second word line for second and fourth memory cell transistors, first to fourth selection gate lines respectively for first through fourth select transistors, a bit line, and a source line. During a read operation, while a voltage applied to the second word line is boosted, voltages applied to the first word line and the third and fourth selection gate line are also boosted, after which the voltage applied to the first word line is lowered, and the third and fourth selection gate lines are discharged. After the time the third and fourth selection gate lines are discharged, voltages applied to the bit line and the source line are boosted.

公开(公告)号：US12211567B2

公开(公告)日：2025-01-28

申请号：US17816836

申请日：2022-08-02

Applicant: Kioxia Corporation

Inventor： Kazutaka Ikegami ,  Takashi Maeda ,  Reiko Sumi

IPC: G11C16/34 ,  G11C16/04 ,  G11C16/10 ,  G11C16/24 ,  G11C16/26 ,  G11C16/30

Abstract: A memory system according to an embodiment includes a first bit line, a source line, a first word line, a second word line, a first memory pillar and a control circuit. The control circuit performs a first verify operation to first and second memory cells, a second verify operation to the first memory cell, a third verify operation to the second memory cell and a write operation or a read operation with a lower voltage in accordance with a request from an external device.

公开(公告)号：US12211558B2

公开(公告)日：2025-01-28

申请号：US18177730

申请日：2023-03-02

Applicant: Kioxia Corporation

Inventor： Yasuhiro Uchimura

IPC: G11C16/30 ,  G11C16/04 ,  G11C16/16 ,  G11C16/34 ,  H10B41/27 ,  H10B43/27

Abstract: According to one embodiment, in a semiconductor storage device, during an erasing operation, a voltage supplied to at least one of a first wiring and a second wiring is set as a first voltage, and a voltage supplied to a first conductive layer is set as a second voltage. The erasing operation includes a first operation period in which the first voltage is increased from a first reference voltage to a first erase voltage and the second voltage is increased from a second reference voltage to a second erase voltage. In a second operation period of the erasing operation, the first voltage is maintained at the first erase voltage and the second voltage is decreased from the second erase voltage to the second reference voltage (or a first level voltage larger than the second reference voltage) after the first operation period.