公开(公告)号：US12132451B2

公开(公告)日：2024-10-29

申请号：US17583018

申请日：2022-01-24

申请人： Micron Technology, Inc.

发明人： Wei Lu Chu ,  Dong Pan

IPC分类号： H03F1/30 ,  G11C11/4074 ,  H02M3/155 ,  H03F1/02 ,  H03F3/21

CPC分类号： H03F1/301 ,  G11C11/4074 ,  H02M3/155 ,  H03F1/0233 ,  H03F3/211 ,  H03F2200/504

摘要： Systems and devices are provided for tracking bandgap current generated by a bandgap circuit and mitigation of leakage current regardless of variations in PVT conditions. An apparatus may include one or more power amplifiers that powers components of the apparatus and comprising a transistor. The apparatus may also include bandgap current mirroring circuitry that generates a mirrored current that mirrors a received current that is process, voltage, and temperature (PVT) independent. The apparatus may also include a bulk voltage generator circuit including an amplifier having an input coupled to the bandgap current mirroring circuitry. Bulk voltage control circuitry is coupled to an output of the amplifier and generates a bulk voltage based on the relationship between the mirrored current and the leakage current.

公开(公告)号：US20240331759A1

公开(公告)日：2024-10-03

申请号：US18594666

申请日：2024-03-04

申请人： Lodestar Licensing Group LLC

发明人： Alberto Troia

IPC分类号： G11C11/409 ,  G06F9/30 ,  G06N3/04 ,  G06N3/06 ,  G11C8/12 ,  G11C11/4074

CPC分类号： G11C11/409 ,  G06F9/30101 ,  G06N3/04 ,  G06N3/06 ,  G11C8/12 ,  G11C11/4074

摘要： The present disclosure includes apparatuses and methods related to an artificial intelligence accelerator in memory. An example apparatus can include a number of registers configured to enable the apparatus to operate in an artificial intelligence mode to perform artificial intelligence operations and an artificial intelligence (AI) accelerator configured to perform the artificial intelligence operations using the data stored in the number of memory arrays. The AI accelerator can include hardware, software, and or firmware that is configured to perform operations associated with AI operations. The hardware can include circuitry configured as an adder and/or multiplier to perform operations, such as logic operations, associated with AI operations.

公开(公告)号：US20240321341A1

公开(公告)日：2024-09-26

申请号：US18593233

申请日：2024-03-01

申请人： Kioxia Corporation

发明人： Katsuaki SAKURAI ,  Daisuke ARIZONO ,  Mitsuhiro ABE ,  Yasuhiro HIRASHIMA

IPC分类号： G11C11/4096 ,  G11C11/4074 ,  G11C11/4091

CPC分类号： G11C11/4096 ,  G11C11/4074 ,  G11C11/4091

摘要： A storage device includes a memory cell array, an input/output circuit, and a logic circuit. The input/output circuit including an input/output signal line through which data to be written into the memory cell array is received and data read from the memory cell array is transmitted. The logic circuit is configured to output a first signal to the input/output circuit. The first signal at an active level enables at least a part of the input/output circuit. The logic circuit includes a latch circuit configured to output a second signal at a level corresponding to a value of latched data. The logic circuit receives third, fourth, and fifth signals from an outside of the storage device via the input/output circuit. The logic circuit outputs a negative logical product of the third signal and a logical sum of at least the second, fourth, and fifth signals as the first signal.

公开(公告)号：US20240312543A1

公开(公告)日：2024-09-19

申请号：US18672623

申请日：2024-05-23

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Yih WANG ,  Hiroki NOGUCHI

IPC分类号： G11C17/12 ,  G11C11/4074 ,  G11C11/408 ,  G11C11/4094 ,  G11C17/16 ,  H01L21/8234

CPC分类号： G11C17/12 ,  G11C11/4074 ,  G11C11/4085 ,  G11C11/4094 ,  G11C17/16 ,  H01L21/823425

摘要： Various one-time-programmable (OTP) memory cells are disclosed. An OTP memory cell includes an additional dopant region that extends at least partially under the gate of a transistor, such as an anti-fuse transistor. The additional dopant region provides an additional current path for a read current. Alternatively, an OTP memory cell includes three transistors; an anti-fuse transistor and two select transistors. The two select transistors can be configured as a cascaded select transistor or as two separate select transistors.

公开(公告)号：US20240312501A1

公开(公告)日：2024-09-19

申请号：US18675770

申请日：2024-05-28

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

发明人： Shang-Chi WU ,  Yangsyu LIN ,  Chiting CHENG ,  Jonathan Tsung-Yung CHANG ,  Mahmut SINANGIL

IPC分类号： G11C7/12 ,  G11C11/4074 ,  G11C11/4094 ,  G11C11/412 ,  G11C11/413 ,  G11C11/419

CPC分类号： G11C7/12 ,  G11C11/413 ,  G11C11/4074 ,  G11C11/4094 ,  G11C11/412 ,  G11C11/419

摘要： A memory circuit includes a control circuit, a memory cell column, first and second bit lines coupled to the memory cell column, a write circuit coupled to a first end of each of the first and second bit lines, and a switching circuit including a first NAND gate including an input terminal coupled to the control circuit, an input terminal coupled to the first bit line, and a first output terminal, a first PMOS transistor coupled between a power supply node and the first bit line and including a gate coupled to the first output terminal, a second NAND gate including an input terminal coupled to the control circuit, an input terminal coupled to the second bit line, and a second output terminal, and a second PMOS transistor coupled between the power supply node and the second bit line and including a gate coupled to the second output terminal.

公开(公告)号：US12087348B2

公开(公告)日：2024-09-10

申请号：US17766326

申请日：2020-11-06

申请人： TOBB EKONOMI VE TEKNOLOJI UNIVERSITESI

发明人： Fahrettin Koc ,  Oguz Ergin

IPC分类号： G11C11/24 ,  G11C11/4074

CPC分类号： G11C11/4074

摘要： Disclosed is an adaptive application of bias voltages to the access transistors in the cells in dynamic random access memory (DRAM) structures, according to the access pattern of the rows, in other words, whether the rows are accessed and/or how often rows are accessed.

公开(公告)号：US20240282354A1

公开(公告)日：2024-08-22

申请号：US18590221

申请日：2024-02-28

申请人： Rambus Inc.

发明人： Wayne F. Ellis ,  Wayne S. Richardson ,  Akash Bansal ,  Frederick A. Ware ,  Lawrence Lai ,  Kishore Ven Kasamsetty

IPC分类号： G11C11/406 ,  G06F1/3234 ,  G11C7/02 ,  G11C7/20 ,  G11C11/4072 ,  G11C11/4074 ,  G11C29/02

CPC分类号： G11C11/40615 ,  G06F1/3234 ,  G11C7/02 ,  G11C7/20 ,  G11C11/4072 ,  G11C11/4074 ,  G11C29/022 ,  G11C29/028

摘要： In one embodiment, a memory device includes a memory core and input receivers to receive commands and data. The memory device also includes a register to store a value that indicates whether a subset of the input receivers are powered down in response to a control signal. A memory controller transmits commands and data to the memory device. The memory controller also transmits the value to indicate whether a subset of the input receivers of the memory device are powered down in response to the control signal. In addition, in response to a self-fresh command, the memory device defers entry into a self-refresh operation until receipt of the control signal that is received after receiving the self-refresh command.

公开(公告)号：US12061518B2

公开(公告)日：2024-08-13

申请号：US18108876

申请日：2023-02-13

申请人： Micron Technology, Inc.

发明人： Sai Krishna Mylavarapu ,  Todd A. Marquart

IPC分类号： G06F11/10 ,  G11C11/00 ,  G11C11/4074 ,  G11C11/4096

CPC分类号： G06F11/1004 ,  G06F11/1068 ,  G11C11/005 ,  G11C11/4074 ,  G11C11/4096

摘要： Methods, devices, and systems related to storing parity data in dynamic random access memory (DRAM) are described. In an example, a method can include generating, at a controller, parity data based on user data queued for writing to a non-volatile memory device, receiving the parity data at a DRAM device from the controller and writing the parity data to the DRAM device, receiving the user data at a non-volatile memory device from the controller and writing the user data to the non-volatile memory device, reading the user data from the non-volatile memory device via the controller, and receiving the parity data at the controller from the DRAM device.

公开(公告)号：US12056007B2

公开(公告)日：2024-08-06

申请号：US17702291

申请日：2022-03-23

申请人： SAMSUNG ELECTRONICS CO., LTD.

发明人： Eun Chu Oh ,  Junyeong Seok ,  Younggul Song ,  Byungchul Jang

IPC分类号： G06F11/10 ,  G06F11/07 ,  G11C11/4074 ,  G11C11/408 ,  G11C11/4096

CPC分类号： G06F11/1068 ,  G06F11/076 ,  G11C11/4074 ,  G11C11/4082 ,  G11C11/4085 ,  G11C11/4087 ,  G11C11/4096

摘要： A storage device includes a NAND flash memory device, an auxiliary memory device and a storage controller to control the NAND flash memory device and the auxiliary memory device. The storage controller includes a processor, an error correction code (ECC) engine and a memory interface. The processor executes a flash translation layer (FTL) loaded onto an on-chip memory. The ECC engine generates first parity bits for user data to be stored in a target page of the NAND flash memory device based on error attribute of a target memory region associated with the target page, and selectively generates additional parity bits for the user data under control of the processor. The memory interface transmits the user data and the first parity bits to the NAND flash memory device, and selectively transmits the additional parity bits to the auxiliary memory device.

公开(公告)号：US20240249106A1

公开(公告)日：2024-07-25

申请号：US18624312

申请日：2024-04-02

申请人： Kioxia Corporation

发明人： Akihisa FUJIMOTO ,  Toshitada SAITO ,  Noriya SAKAMOTO ,  Atsushi KONDO

IPC分类号： G06K19/077 ,  G11C5/06 ,  G11C11/4074 ,  G11C16/02 ,  G11C16/30

CPC分类号： G06K19/07732 ,  G06K19/07733 ,  G06K19/07743 ,  G11C5/06 ,  G11C11/4074 ,  G11C16/02 ,  G11C16/30

摘要： According to one embodiment, there is provided a memory card including a first surface, a second surface, and 1st to Nth terminal groups. The first surface includes first to Nth rows, where N is an integer of two or greater. The second surface faces the opposite side from the first surface. The 1st to Nth terminal groups are placed in the first to Nth rows. The 1st terminal group includes terminals to which differential clock signals are assigned, terminals to which single-ended signals are assigned, and a terminal to which a first power supply voltage is assigned. Kth terminal group, where K is an integer no smaller than two and no greater than N, includes terminals to which differential data signals are assigned.