公开(公告)号：US20240223207A1

公开(公告)日：2024-07-04

申请号：US18148259

申请日：2022-12-29

申请人： ROBERT BOSCH GMBH

发明人： Kenneth Edward WOJCIECHOWSKI ,  Sangwoo LEE

IPC分类号： H03M1/46 ,  G06F7/544 ,  G06F9/30 ,  G11C11/413 ,  H03M1/80

CPC分类号： H03M1/462 ,  G06F7/5443 ,  G06F9/3001 ,  G11C11/413 ,  H03M1/804 ,  G06F2207/4812 ,  G06F2207/4824

摘要： A multiply-accumulate successive approximation (MASAR) column is provided. The MASAR column includes a plurality of MASAR cells, each including a multiplier configured to perform digital multiplication between an input activation received to an input and an operand to compute a result, and a unit capacitor configured to store the result as analog charge. The MASAR column further includes digital logic configured to perform analog summation of the analog charge of the unit capacitors of the plurality of MASAR cells to determine a digital output of the multiplication.

公开(公告)号：US12014771B2

公开(公告)日：2024-06-18

申请号：US18175023

申请日：2023-02-27

申请人： QUALCOMM Incorporated

发明人： Changho Jung ,  Arun Babu Pallerla ,  Chulmin Jung

IPC分类号： G11C11/419 ,  G11C11/413 ,  H03K19/20

CPC分类号： G11C11/419 ,  G11C11/413 ,  H03K19/20

摘要： A pseudo-triple-port memory is provided with read datapaths and write datapaths. The pseudo-triple-port memory includes a plurality of pseudo-triple-port bitcells, each pseudo-triple-port first bitcell having a first read port coupled to a first bit line, a second read port coupled to a second bit line, and a write port coupled to the first bit line and to the second bit line.

公开(公告)号：US11900993B2

公开(公告)日：2024-02-13

申请号：US17637312

申请日：2020-08-13

申请人： SONY SEMICONDUCTOR SOLUTIONS CORPORATION

发明人： Yusuke Shuto

IPC分类号： G11C11/413 ,  G11C11/412 ,  G11C11/16 ,  H03K3/037

CPC分类号： G11C11/413 ,  G11C11/412 ,  G11C11/1697 ,  H03K3/037

摘要： A semiconductor circuit according to the present disclosure includes: a first circuit configured to apply an inverted voltage of a voltage at a first node to a second node; a second circuit configured to apply an inverted voltage of a voltage at a second node to the first node; a first storage element including first, second, and third terminals; a first transistor including a drain coupled to the first node and a source coupled to the first terminal of the first storage element; a second transistor including a gate coupled to the first node or the second node and a drain coupled to the second terminal of the first storage element; and a third transistor including a gate coupled to the first node or the second node and a drain coupled to the second terminal of the first storage element. The first storage element is configured to set a resistance state between the first terminal and the second and third terminals in accordance with a direction of a current flowing between the second and third terminals.

公开(公告)号：US11862286B2

公开(公告)日：2024-01-02

申请号：US17649068

申请日：2022-01-27

申请人： CHANGXIN MEMORY TECHNOLOGIES, INC.

发明人： Liang Zhang

IPC分类号： G11C7/10 ,  G11C11/413

CPC分类号： G11C7/1057 ,  G11C7/1069 ,  G11C7/1084 ,  G11C7/1096 ,  G11C11/413

摘要： A data transmission circuit includes: a comparison circuit, configured to compare received first data on a data bus with received second data on a global data line and output a comparison result of whether a number of different bits between the first data and the second data exceeds a preset threshold; a data conversion circuit, configured to: if the comparison result indicates that the number of different bits exceeds the preset threshold, invert the first data and transmit the inverted first data to the global data line, and otherwise, transmit the first data to the global data line; and a read-write conversion circuit, configured to: if the comparison result indicates that the number of different bits exceeds the preset threshold, transmit data on the global data line to a complementary local data line, and otherwise, transmit data on the global data line to a local data line.

公开(公告)号：US20230343388A1

公开(公告)日：2023-10-26

申请号：US18340214

申请日：2023-06-23

申请人： SK hynix Inc.

发明人： Nam Jae LEE

IPC分类号： G11C11/413

CPC分类号： G11C11/413 ,  H10B10/00

摘要： There are provided a semiconductor memory device and a manufacturing method thereof. The semiconductor memory device includes: a source layer; a channel structure extending in a first direction from within the source layer; a source-channel contact layer surrounding the channel structure on the source layer; a first select gate layer overlapping with the source-channel contact layer and surrounding the channel structure; a stack including interlayer insulating layers and conductive patterns that are alternately stacked in the first direction and surrounding the channel structure, the stack overlapping with the first select gate layer; and a first insulating pattern that is formed thicker between the first select gate layer and the channel structure than between the stack and the channel structure.

公开(公告)号：US20230326505A1

公开(公告)日：2023-10-12

申请号：US18336418

申请日：2023-06-16

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

发明人： Tsung-Hsien HUANG ,  Wei-Jer HSIEH ,  Yu-Hao HSU

IPC分类号： G11C8/18 ,  H03K19/017 ,  G11C11/413 ,  G11C11/419 ,  G11C11/412 ,  G11C8/08

CPC分类号： G11C8/18 ,  H03K19/01742 ,  G11C11/413 ,  G11C11/419 ,  G11C11/412 ,  G11C8/08 ,  G11C7/12

摘要： A memory device including a first memory cell, a first tracking cell, a tracking bit line, a second tracking cell and a word line driver. The first memory cell is configured to receive a first word line signal. The first tracking cell is configured to emulate the first memory cell. The tracking bit line is configured to transmit a tracking bit line signal to the first tracking cell. The second tracking cell is configured to adjust the tracking bit line signal according to the first word line signal. The word line driver is configured to adjust the first word line signal according to the tracking bit line signal and a first distance between the second tracking cell and a common node on the tracking bit line.

公开(公告)号：US11749321B2

公开(公告)日：2023-09-05

申请号：US17408567

申请日：2021-08-23

申请人： Taiwan Semiconductor Manufacturing Company Limited

发明人： Wei-Cheng Wu ,  Kao-Cheng Lin ,  Chih-Cheng Yu ,  Pei-Yuan Li ,  Chien-Chen Lin ,  Wei Min Chan ,  Yen-Huei Chen

IPC分类号： G11C7/12 ,  G11C11/419 ,  G11C7/10 ,  G11C11/4093 ,  G11C11/4091 ,  G11C11/4094 ,  G11C11/4076 ,  G11C11/416 ,  G11C11/413 ,  G11C11/4096

CPC分类号： G11C7/12 ,  G11C7/1048 ,  G11C11/4076 ,  G11C11/4091 ,  G11C11/4093 ,  G11C11/4094 ,  G11C11/4096 ,  G11C11/413 ,  G11C11/416 ,  G11C11/419

摘要： Systems and method are provided for a memory circuit that includes a bit cell responsive to a bit line signal line and a bit line bar signal line configured to store a bit of data. A pre-charge circuit is configured to charge one of the bit line and bit line bar signal lines prior to a read operation, where the pre-charge circuit includes a first pre-charge component and a second pre-charge component, the first and second pre-charge components being individually controllable for charging the bit line and bit line bar signal lines.

公开(公告)号：US20230259751A1

公开(公告)日：2023-08-17

申请号：US18139760

申请日：2023-04-26

申请人： UNIVERSITY OF SOUTHAMPTON

发明人： Alexantrou SERB ,  Themistoklis PRODROMAKIS

IPC分类号： G06N3/065 ,  G06N3/049 ,  G11C11/413 ,  G11C11/54 ,  H03K19/20

CPC分类号： G06N3/065 ,  G06N3/049 ,  G11C11/413 ,  G11C11/54 ,  H03K19/20

摘要： A tunable CMOS circuit comprising a CMOS element and a tunable load. The CMOS element is configured to receive an analogue input signal. The tunable load is connected to the CMOS element and configured to set a switch point of the CMOS element. The CMOS element is configured to output an output current that is largest when the analogue input signal is equal to the switch point. The combination of a CMOS element with a tunable load may also provide a hardware implementation of fuzzy logic. A fuzzy logic gate comprises an input node, a CMOS logic gate, a tunable load, and an output node. The input node is configured to receive an analogue input signal. The CMOS logic gate is connected to the input node. The tunable load is connected to the CMOS logic gate such that the tunable load is provided on a current path connected to the output node. The output node is configured to output an analogue output signal.

公开(公告)号：US11705189B2

公开(公告)日：2023-07-18

申请号：US17473648

申请日：2021-09-13

申请人： SK hynix Inc.

发明人： Nam Jae Lee

IPC分类号： H01L27/115 ,  G11C11/413 ,  H10B10/00

CPC分类号： G11C11/413 ,  H10B10/00

摘要： There are provided a semiconductor memory device and a manufacturing method thereof. The semiconductor memory device includes: a source layer; a channel structure extending in a first direction from within the source layer; a source-channel contact layer surrounding the channel structure on the source layer; a first select gate layer overlapping with the source-channel contact layer and surrounding the channel structure; a stack including interlayer insulating layers and conductive patterns that are alternately stacked in the first direction and surrounding the channel structure, the stack overlapping with the first select gate layer; and a first insulating pattern that is formed thicker between the first select gate layer and the channel structure than between the stack and the channel structure.

公开(公告)号：US11682452B2

公开(公告)日：2023-06-20

申请号：US17480191

申请日：2021-09-21

申请人： International Business Machines Corporation

发明人： Antonio Pelella ,  Dongho Lee ,  Genadi Tverskoy ,  Zhiying Chen ,  Brian James Yavoich

IPC分类号： G11C7/12 ,  G11C11/412 ,  H03K19/017 ,  G11C11/419 ,  G11C11/413 ,  G11C7/10

CPC分类号： G11C11/412 ,  G11C11/413 ,  G11C11/419 ,  H03K19/01742 ,  G11C7/1078 ,  G11C2207/002

摘要： Aspects of the invention include a first pull-down device and a second pull-down device, wherein a first drain terminal is connected to a second source terminal, and wherein a first gate terminal is connected to a true read local bitline, wherein a second drain terminal is connected to a compliment read local bit line, and wherein a second gate terminal is connected to a true write global bitline, a third pull-down device and a fourth pull-down device, wherein a third source terminal is connected to the voltage supply, wherein a third drain terminal is connected to a fourth source terminal, and wherein a third gate terminal is connected to the compliment read local bitline, and wherein a fourth drain terminal is connected to the true read local bitline, and wherein a fourth gate terminal is connected to a compliment write global bit line.