公开(公告)号：US20250069650A1

公开(公告)日：2025-02-27

申请号：US18744498

申请日：2024-06-14

Applicant: Shanghai Huali Integrated Circuit Corporation

Inventor： Pinhan CHEN ,  Gang LI

IPC: G11C11/412 ,  G11C11/419 ,  H10B10/00

Abstract: The present application discloses a three-port SRAM circuit, which is formed by adding two read ports to a six-transistor single-port SRAM circuit. Storage states of a first node and a second node of the six-transistor single-port SRAM circuit are opposite, so that a third P-type transistor with a gate terminal thereof corresponding to the first node and a fifth N-type transistor with a gate terminal thereof corresponding to the second node can be on/off synchronously. When a sixth N-type transistor and a fourth P-type transistor are both on, a port C bit line and a port B bit line can be held/discharge synchronously, so as to facilitate a system operating a peripheral circuit simultaneously when reading ports B and C at high speeds.

公开(公告)号：US20250056784A1

公开(公告)日：2025-02-13

申请号：US18448581

申请日：2023-08-11

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Jhon-Jhy LIAW

IPC: H10B10/00 ,  G11C11/412

Abstract: A memory device includes a first static random-access memory (SRAM) array having first SRAM cell groups arranged in an X-direction and a second SRAM array having second SRAM cell groups arranged in the X-direction. Each of the first SRAM cell groups includes two adjacent first SRAM cells arranged in the X-direction. Each of the first SRAM cells includes a first bit-line conductor and a first bit-line-bar conductor extending in a Y-direction. Each of the second SRAM cell groups includes two adjacent second SRAM cells arranged in the X-direction and sharing a second bit-line conductor and a second bit-line-bar conductor extending in the Y-direction. A first cell size of the first SRAM cells is larger than a second cell size of the second SRAM cells.

公开(公告)号：US20250040228A1

公开(公告)日：2025-01-30

申请号：US18916723

申请日：2024-10-16

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chun-Hsien Huang ,  Yu-Tse Kuo ,  Shu-Ru Wang ,  Chien-Hung Chen ,  Li-Ping Huang ,  Chun-Yen Tseng

IPC: H01L29/423 ,  G11C5/06 ,  G11C11/412 ,  H01L29/78 ,  H10B10/00

Abstract: The present invention provides a method for forming a layout pattern of static random access memory, comprising forming a PU1 (first pull-up transistor), a PU2 (second pull-up transistor), a PD1A (first pull-down transistor), a PD1B (second pull-down transistor), a PD2A (third pull-down transistor), a PD2B (fourth pull-down transistor), a PG1A (first access transistor), a PG1B (second access transistor), a PG2A (third access transistor) and a PG2B (fourth access transistor) located on the substrate. The PD1A and the PD1B are connected in parallel with each other, the PD2A and the PD2B are connected in parallel with each other, wherein the gate structures include a first J-shaped gate structure, and the first J-shaped gate structure is an integrally formed structure.

公开(公告)号：US12213298B2

公开(公告)日：2025-01-28

申请号：US17556910

申请日：2021-12-20

Applicant: SOCIONEXT INC.

Inventor： Masanobu Hirose

IPC: H10B10/00 ,  G11C5/02 ,  G11C5/06 ,  G11C11/412 ,  H01L29/06 ,  H01L29/423

Abstract: Transistors (N3, N4) corresponding to a drive transistor (PD1), transistors (N5, N6) corresponding to a drive transistor (PD2), transistors (N7, N8) corresponding to an access transistor (PG1), and transistors (N1, N2) corresponding to an access transistor (PG2) are formed in a lower portion of a cell. Transistors (P1, P2) corresponding to load transistors (PU1, PU2), respectively, are formed in an upper portion of the cell. Further, the transistors (P1, P2) overlap the transistors (N3, N6) in plan view.

公开(公告)号：US12176025B2

公开(公告)日：2024-12-24

申请号：US17844955

申请日：2022-06-21

Applicant: STMicroelectronics International N.V.

Inventor： Harsh Rawat ,  Kedar Janardan Dhori ,  Promod Kumar ,  Nitin Chawla ,  Manuj Ayodhyawasi

IPC: G11C11/412 ,  G11C11/418 ,  G11C11/419

Abstract: An in-memory computation circuit includes a memory array with SRAM cells connected in rows by word lines and in columns by bit lines. Body bias nodes of the transistors in each SRAM cell are biased by a modulated body bias voltage. A row controller circuit simultaneously actuates word lines in parallel for an in-memory compute operation. A column processing circuit processes analog voltages developed on the bit lines in response to the simultaneous actuation to generate a decision output for the in-memory compute operation. A voltage generator circuit switches the modulated body bias voltage from a non-negative voltage level to a negative voltage level during the simultaneous actuation. The negative voltage level is adjusted dependent on integrated circuit process and/or temperature conditions in order to optimize protection against unwanted memory cell data flip.

公开(公告)号：US12176024B2

公开(公告)日：2024-12-24

申请号：US18233985

申请日：2023-08-15

Applicant: Zeno Semiconductor, Inc.

Inventor： Jin-Woo Han ,  Yuniarto Widjaja

IPC: G11C11/417 ,  G11C11/404 ,  G11C11/4091 ,  G11C11/412 ,  G11C15/04 ,  H10B12/00

Abstract: A memory cell comprising includes a silicon-on-insulator (SOI) substrate, an electrically floating body transistor fabricated on the silicon-on-insulator (SOI) substrate, and a charge injector region. The floating body transistor is configured to have more than one stable state through an application of a bias on the charge injector region.

公开(公告)号：US20240414906A1

公开(公告)日：2024-12-12

申请号：US18494073

申请日：2023-10-25

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Ping-Wei Wang ,  Jui-Lin Chen

IPC: H10B10/00 ,  G11C11/412 ,  H01L23/522 ,  H01L23/528

Abstract: A memory cell includes first and second active regions and first and second gate structures. The first gate structure engages the first active region in forming a first transistor. The second gate structure engages the second active region in forming a second transistor. The first and second transistors have a same conductivity type. The memory cell further includes a first epitaxial feature on a source region of the first transistor, a second epitaxial feature on a source region of the second transistor, a first frontside contact directly above and in electrical coupling with the first epitaxial feature, a second frontside contact directly above and in electrical coupling with the second epitaxial feature, and a first backside via directly under and in electrical coupling with one of the first and second epitaxial features with another one of the first and second epitaxial features free of a backside via directly thereunder.

公开(公告)号：US12165698B2

公开(公告)日：2024-12-10

申请号：US17483501

申请日：2021-09-23

Applicant: STMicroelectronics International N.V.

Inventor： Kedar Janardan Dhori

IPC: G11C11/417 ,  G11C11/412

Abstract: A static random access memory (SRAM) device disclosed herein includes an array of SRAM cells powered between first and second voltages. A reference voltage generator generates a reference voltage that is proportional to absolute temperature, with a magnitude curve of the reference voltage being based upon a control word. A low dropout amplifier sets and maintains the second voltage as being equal to the reference voltage. Control circuitry generates the control word based upon process variation information about the SRAM device. In one instance, the control circuitry monitors a canary bit-cell and increments the control word, to thereby increase the magnitude curve of the reference voltage, until the canary bit-cell fails. In another instance, the control circuitry measures the oscillation frequency of a ring oscillator, and selects the control word based upon the measured oscillation frequency.

公开(公告)号：US20240385803A1

公开(公告)日：2024-11-21

申请号：US18788483

申请日：2024-07-30

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Po-Hao Lee ,  Chia-Fu Lee ,  Yi-Chun Shih ,  Yu-Der Chih ,  Hidehiro Fujiwara ,  Haruki Mori ,  Wei-Chang Zhao

IPC: G06F7/544 ,  G11C11/412

Abstract: A compute-in-memory (CIM) device has a memory array with a plurality of memory cells arranged in rows and columns. The plurality of memory cells includes a first memory cell in a first row and a first column of the memory array and a second memory cell in the first row and a second column of the memory array. The first and second memory cells are configured to store respective first and second weight signals. An input driver provides a plurality of input signals. A first logic circuit is coupled to the first memory cell to provide a first output signal based on a first input signal from the input driver and the first weight signal. A second logic circuit is coupled to the second memory cell to provide a second output signal based on a second input signal from the input driver and the second weight signal.

公开(公告)号：US12148463B2

公开(公告)日：2024-11-19

申请号：US17671288

申请日：2022-02-14

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Jhon Jhy Liaw

IPC: G11C11/412 ,  H10B10/00

Abstract: A dual-port memory cell includes first pull-up and pull-down transistors coupled at a first node between supply and reference voltage nodes, second pull-up and pull-down transistors coupled at a second node between the supply and reference voltage nodes, and first through fourth bit line landing pads in a metal layer. A first pass-gate transistor is coupled between the first bit line landing pad and the first node, a second pass-gate transistor is coupled between the second bit line landing pad and the second node, a third pass-gate transistor is coupled between the third bit line landing pad and the first node, and a fourth pass-gate transistor is coupled between the fourth bit line landing pad and the second node. The first node includes an interconnect between the first and second bit line landing pads, and the second node includes an interconnect between the third and fourth bit line landing pads.