公开(公告)号：US10050044B2

公开(公告)日：2018-08-14

申请号：US15422471

申请日：2017-02-02

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Li-Ping Huang ,  Chun-Hsien Huang ,  Yu-Tse Kuo ,  Ching-Cheng Lung

IPC: H01L27/11 ,  H01L27/092 ,  G11C11/412 ,  G11C7/14 ,  G11C11/419 ,  H01L27/02 ,  G11C7/22 ,  H01L27/105 ,  G11C7/02

CPC classification number: H01L27/1104 ,  G11C7/02 ,  G11C7/14 ,  G11C7/22 ,  G11C11/4125 ,  H01L27/02 ,  H01L27/092 ,  H01L27/0924 ,  H01L27/105 ,  H01L27/1116

Abstract: The present invention proposes a static random-access memory device (SRAM). The static random-access memory device is composed of two P-channel gates of loading transistor, two N-channel gates of driving transistor and two N-channel gates of accessing transistor in a memory cell. A dummy gate is disposed adjacent to the N-channel gate of accessing transistor with a bit line node disposed therebetween, wherein the dummy gate is electrically connected to a ground voltage through a metal layer.

公开(公告)号：US09786647B1

公开(公告)日：2017-10-10

申请号：US15092630

申请日：2016-04-07

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chun-Hsien Huang ,  Yung-Feng Cheng ,  Yu-Tse Kuo ,  Chia-Wei Huang ,  Li-Ping Huang ,  Shu-Ru Wang

IPC: H01L23/528 ,  H01L23/522 ,  H01L27/11 ,  H01L27/02

CPC classification number: H01L27/0207 ,  H01L23/5226 ,  H01L23/528 ,  H01L27/1104

Abstract: A semiconductor layout structure includes a substrate comprising a cell edge region and a dummy region abutting thereto, a plurality of dummy contact patterns disposed in the dummy region and arranged along a first direction, and a plurality of dummy gate patterns disposed in the dummy region and arranged along the first direction. The dummy contact patterns and the dummy gate patterns are alternately arranged. Each dummy contact pattern includes an inner dummy contact proximal to the cell edge region and an outer dummy contact distal to the cell edge region, and the inner dummy contact and the outer dummy contact are arranged along a second direction perpendicular to the first direction and spaced apart from each other by a first gap.

公开(公告)号：US20250040228A1

公开(公告)日：2025-01-30

申请号：US18916723

申请日：2024-10-16

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chun-Hsien Huang ,  Yu-Tse Kuo ,  Shu-Ru Wang ,  Chien-Hung Chen ,  Li-Ping Huang ,  Chun-Yen Tseng

IPC: H01L29/423 ,  G11C5/06 ,  G11C11/412 ,  H01L29/78 ,  H10B10/00

Abstract: The present invention provides a method for forming a layout pattern of static random access memory, comprising forming a PU1 (first pull-up transistor), a PU2 (second pull-up transistor), a PD1A (first pull-down transistor), a PD1B (second pull-down transistor), a PD2A (third pull-down transistor), a PD2B (fourth pull-down transistor), a PG1A (first access transistor), a PG1B (second access transistor), a PG2A (third access transistor) and a PG2B (fourth access transistor) located on the substrate. The PD1A and the PD1B are connected in parallel with each other, the PD2A and the PD2B are connected in parallel with each other, wherein the gate structures include a first J-shaped gate structure, and the first J-shaped gate structure is an integrally formed structure.

公开(公告)号：US20230197153A1

公开(公告)日：2023-06-22

申请号：US17580591

申请日：2022-01-20

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chun-Yen Tseng ,  Yu-Tse Kuo ,  Shu-Ru Wang ,  Chun-Hsien Huang ,  Hsin-Chih Yu ,  Meng-Ping Chuang ,  Li-Ping Huang ,  Yu-Fang Chen

IPC: G11C15/04

CPC classification number: G11C15/04

Abstract: A layout of a semiconductor memory device includes a substrate and a ternary content addressable memory (TCAM). The TCAM is disposed on the substrate and includes a plurality of TCAM bit cells, where at least two of the TCAM bit cells are mirror-symmetrical along an axis of symmetry, and each of the TCAM bit cells includes two storage units electrically connected to two word lines respectively, and a logic circuit electrically connected to the storage units. The logic circuit includes two first reading transistors, and two second reading transistors, where each of the second reading transistors includes a gate and source and drain regions, the source and drain regions of the second reading transistors are electrically connected to two matching lines and the first reading transistors, respectively, where the word lines are disposed parallel to and between the matching lines.

公开(公告)号：US10026726B2

公开(公告)日：2018-07-17

申请号：US15604685

申请日：2017-05-25

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Ching-Wen Hung ,  Chih-Sen Huang ,  Shih-Fang Tzou ,  Yi-Wei Chen ,  Yung-Feng Cheng ,  Li-Ping Huang ,  Chun-Hsien Huang ,  Chia-Wei Huang ,  Yu-Tse Kuo

IPC: H01L21/8238 ,  H01L21/768 ,  H01L27/11 ,  H01L29/78 ,  H01L29/66 ,  H01L27/092 ,  H01L27/02

Abstract: Semiconductor devices and method of manufacturing such semiconductor devices are provided for improved FinFET memory cells to avoid electric short often happened between metal contacts of a bit cell, where the meal contacts are positioned next to a dummy gate of a neighboring dummy edge cell. In one embodiment, during the patterning of a gate layer on a substrate surface, an improved gate slot pattern is used to extend the lengths of one or more gate slots adjacent bit lines so as to pattern and sectionalize a dummy gate line disposed next to metal contacts of an active memory cell. In another embodiment, during the patterning of gate lines, the distances between one or more dummy gates lines disposed adjacent an active memory cell are adjusted such that their locations within dummy edge cells are shifted in position to be away from metal contacts of the active memory cell.

公开(公告)号：US20170263597A1

公开(公告)日：2017-09-14

申请号：US15604685

申请日：2017-05-25

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Ching-Wen Hung ,  Chih-Sen Huang ,  Shih-Fang Tzou ,  Yi-Wei Chen ,  Yung-Feng Cheng ,  Li-Ping Huang ,  Chun-Hsien Huang ,  Chia-Wei Huang ,  Yu-Tse Kuo

IPC: H01L27/02 ,  H01L21/8238 ,  H01L29/66 ,  H01L21/768 ,  H01L27/11 ,  H01L27/092

CPC classification number: H01L27/0207 ,  H01L21/768 ,  H01L21/76816 ,  H01L21/76829 ,  H01L21/823821 ,  H01L21/823871 ,  H01L27/0924 ,  H01L27/1104 ,  H01L29/66545 ,  H01L29/6681 ,  H01L29/7851

Abstract: Semiconductor devices and method of manufacturing such semiconductor devices are provided for improved FinFET memory cells to avoid electric short often happened between metal contacts of a bit cell, where the meal contacts are positioned next to a dummy gate of a neighboring dummy edge cell. In one embodiment, during the patterning of a gate layer on a substrate surface, an improved gate slot pattern is used to extend the lengths of one or more gate slots adjacent bit lines so as to pattern and sectionalize a dummy gate line disposed next to metal contacts of an active memory cell. In another embodiment, during the patterning of gate lines, the distances between one or more dummy gates lines disposed adjacent an active memory cell are adjusted such that their locations within dummy edge cells are shifted in position to be away from metal contacts of the active memory cell.

公开(公告)号：US11915755B2

公开(公告)日：2024-02-27

申请号：US17580591

申请日：2022-01-20

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chun-Yen Tseng ,  Yu-Tse Kuo ,  Shu-Ru Wang ,  Chun-Hsien Huang ,  Hsin-Chih Yu ,  Meng-Ping Chuang ,  Li-Ping Huang ,  Yu-Fang Chen

IPC: G11C15/04

CPC classification number: G11C15/04

Abstract: A layout of a semiconductor memory device includes a substrate and a ternary content addressable memory (TCAM). The TCAM is disposed on the substrate and includes a plurality of TCAM bit cells, where at least two of the TCAM bit cells are mirror-symmetrical along an axis of symmetry, and each of the TCAM bit cells includes two storage units electrically connected to two word lines respectively, and a logic circuit electrically connected to the storage units. The logic circuit includes two first reading transistors, and two second reading transistors, where each of the second reading transistors includes a gate and source and drain regions, the source and drain regions of the second reading transistors are electrically connected to two matching lines and the first reading transistors, respectively, where the word lines are disposed parallel to and between the matching lines.

公开(公告)号：US20230282261A1

公开(公告)日：2023-09-07

申请号：US17707934

申请日：2022-03-29

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chun-Yen Tseng ,  Yu-Tse Kuo ,  Shu-Ru Wang ,  Jen-Yu Wang ,  Li-Ping Huang ,  Yi-Ting Wu ,  Jia-Rong Wu ,  Chun-Hsien Huang

IPC: G11C11/16 ,  H01L43/02 ,  H01L43/08 ,  H01L27/22

CPC classification number: G11C11/161 ,  G11C11/1655 ,  G11C11/1657 ,  G11C11/1673 ,  G11C11/1675 ,  H01L27/228 ,  H01L43/02 ,  H01L43/08

Abstract: The present invention provides a spin-orbit torque magnetic random access memory (SOT-MRAM) circuit, including a read transistor pair with two read transistors in parallel, a write transistor pair with two write transistors in parallel, a SOT memory cell with a magnetic tunnel junction (MTJ) and a SOT layer, wherein one end of the MTJ is connected to the source of the read transistor pair and the other end of the MTJ is connected to the SOT layer, and one end of the SOT layer is connected to a source line and the other of the SOT layer is connected to the source of the write transistor pair, a read bit line is connected to the drain of the read transistor pair and a write bit line is connected to the drain of the read transistor.

公开(公告)号：US20230207648A1

公开(公告)日：2023-06-29

申请号：US17583225

申请日：2022-01-25

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chun-Hsien Huang ,  Yu-Tse Kuo ,  Shu-Ru Wang ,  Chien-Hung Chen ,  Li-Ping Huang ,  Chun-Yen Tseng

IPC: H01L29/423 ,  H01L27/11 ,  G11C11/412 ,  G11C5/06 ,  H01L29/78

CPC classification number: H01L29/42376 ,  G11C5/063 ,  G11C11/412 ,  H01L27/1104 ,  H01L29/7851

Abstract: The present invention provides a layout pattern of static random access memory, comprising a PU1 (first pull-up transistor), a PU2 (second pull-up transistor), a PD1A (first pull-down transistor), a PD1B (second pull-down transistor), a PD2A (third pull-down transistor), a PD2B (fourth pull-down transistor), a PG1A (first access transistor), a PG1B (second access transistor), a PG2A (third access transistor) and a PG2B (fourth access transistor) located on the substrate. The PD1A and the PD1B are connected in parallel with each other, the PD2A and the PD2B are connected in parallel with each other, wherein the gate structures include a first J-shaped gate structure, and the first J-shaped gate structure is an integrally formed structure.

公开(公告)号：US20240161818A1

公开(公告)日：2024-05-16

申请号：US18071658

申请日：2022-11-30

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chun-Hsien Huang ,  Yu-Tse Kuo ,  Shu-Ru Wang ,  Li-Ping Huang ,  Yu-Fang Chen ,  Chun-Yen Tseng ,  Tzu-Feng Chang ,  Chun-Chieh Chang

IPC: G11C11/412 ,  H01L29/66 ,  H01L29/78 ,  H10B10/00

CPC classification number: G11C11/412 ,  H01L27/1104 ,  H01L29/6681 ,  H01L29/7851

Abstract: The invention provides a layout pattern of static random access memory (SRAM), which at least comprises a plurality of gate structures located on a substrate and spanning the plurality of fin structures to form a plurality of transistors distributed on the substrate, wherein the plurality of transistors comprise two pull-up transistors (PU), two pull-down transistors (PD) to form a latch circuit, and two access transistors (PG) connected to the latch circuit. In each SRAM memory cell, the fin structure included in the pull-up transistor (PU) is defined as a PU fin structure, the fin structure included in the pull-down transistor (PD) is defined as a PD fin structure, and the fin structure included in the access transistor (PG) is defined as a PG fin structure, wherein a width of the PD fin structure is wider than a width of the PG fin structure.