公开(公告)号：US20240365528A1

公开(公告)日：2024-10-31

申请号：US18643224

申请日：2024-04-23

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Changhoon SUNG ,  Hyojin Cho ,  Hoyoung Tang ,  Taehyung Kim ,  Eojin Lee

IPC: H10B10/00 ,  G11C5/06 ,  H01L23/528 ,  H01L27/092 ,  H01L29/06 ,  H01L29/423 ,  H01L29/775 ,  H01L29/78 ,  H01L29/786

CPC classification number: H10B10/125 ,  G11C5/063 ,  H01L23/5283 ,  H01L27/0924 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/775 ,  H01L29/7851 ,  H01L29/78696

Abstract: An integrated circuit is provided and includes a memory cell array, a plurality of gate electrodes extending in a first direction above a substrate, a plurality of word lines extending in the first direction above the substrate, a plurality of bit lines extending below the substrate in a second direction intersecting the first direction, and a plurality of first contacts passing through the substrate in a vertical direction and respectively connected to the plurality of bit lines.

公开(公告)号：US20240363531A1

公开(公告)日：2024-10-31

申请号：US18626935

申请日：2024-04-04

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Soyeon Kim ,  Hoyoung Tang ,  Taehyung Kim

IPC: H01L23/528 ,  G11C5/06 ,  G11C11/419 ,  H01L27/092 ,  H01L29/06 ,  H01L29/423 ,  H01L29/775 ,  H01L29/78 ,  H01L29/786 ,  H10B10/00

CPC classification number: H01L23/5283 ,  G11C5/063 ,  G11C11/419 ,  H01L27/0924 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/775 ,  H01L29/7851 ,  H01L29/78696 ,  H10B10/125

Abstract: Provided is an integrated circuit including a cell array disposed on a substrate and including a plurality of bit cells, a row decoder including a plurality of word line drivers each providing a plurality of word line signals to the cell array, a backside wiring layer disposed on a back side of the substrate to overlap the row decoder and providing power to the plurality of word line drivers, and a plurality of backside contacts between the row decoder and the backside wiring layer. Each of the plurality of backside contacts extends from a source of at least one transistor included in each of the plurality of word line drivers to the backside wiring layer.

公开(公告)号：US20240363439A1

公开(公告)日：2024-10-31

申请号：US18770861

申请日：2024-07-12

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shiu-Ko JANGJIAN ,  Tzu-Kai LIN ,  Chi-Cherng JENG

IPC: H01L21/8238 ,  H01L21/02 ,  H01L21/324 ,  H01L27/092 ,  H01L29/165 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L21/823821 ,  H01L21/02532 ,  H01L21/324 ,  H01L21/823814 ,  H01L27/0924 ,  H01L29/165 ,  H01L29/66636 ,  H01L29/66795 ,  H01L29/7848 ,  H01L29/785

Abstract: A structure and a formation method of a semiconductor device are provided. The semiconductor device includes a semiconductor substrate and a fin structure over the semiconductor substrate. The semiconductor device also includes a gate stack covering a portion of the fin structure and an epitaxially grown source/drain structure over the fin structure and adjacent to the gate stack. The semiconductor device further includes a semiconductor protection layer over the epitaxially grown source/drain structure. The semiconductor protection layer has an atomic concentration of silicon greater than that of the epitaxially grown source/drain structure.

公开(公告)号：US20240363437A1

公开(公告)日：2024-10-31

申请号：US18770367

申请日：2024-07-11

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Shahaji B. MORE

IPC: H01L21/8238 ,  H01L21/02 ,  H01L27/092 ,  H01L29/04 ,  H01L29/08 ,  H01L29/49 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L21/823814 ,  H01L21/02609 ,  H01L21/823821 ,  H01L21/823864 ,  H01L27/0924 ,  H01L29/045 ,  H01L29/0847 ,  H01L29/4983 ,  H01L29/6656 ,  H01L29/66795 ,  H01L29/7851

Abstract: The present disclosure describes a method of forming a semiconductor device having epitaxial structures with optimized dimensions. The method includes forming first and second fin structures on a substrate, forming a spacer layer on the first and second fin structures, forming a first spacer structure adjacent to the first fin structure, and forming a first epitaxial structure adjacent to the first spacer structure. The first and second fin structures are separated by an isolation layer. The first spacer structure has a first height above the isolation layer. The method further includes forming a second spacer structure adjacent to the second fin structure and forming a second epitaxial structure adjacent to the second spacer structure. The second spacer structure has a second height above the isolation layer greater than the first height. The second epitaxial structure includes a type of dopant different from the first epitaxial structure.

公开(公告)号：US20240363352A1

公开(公告)日：2024-10-31

申请号：US18767601

申请日：2024-07-09

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Chandrashekhar Prakash SAVANT ,  Tien-Wei YU ,  Chia-Ming TSAI

IPC: H01L21/28 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/49 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L21/28088 ,  H01L21/823821 ,  H01L21/823842 ,  H01L27/0924 ,  H01L29/4966 ,  H01L29/66795 ,  H01L29/7851

Abstract: The present disclosure describes method to form a semiconductor device with a diffusion barrier layer. The method includes forming a gate dielectric layer on a fin structure, forming a work function stack on the gate dielectric layer, reducing a carbon concentration in the work function stack, forming a barrier layer on the work function stack, and forming a metal layer over the barrier layer. The barrier layer blocks a diffusion of impurities into the work function stack, the gate dielectric layer, and the fin structure.

公开(公告)号：US20240355868A1

公开(公告)日：2024-10-24

申请号：US18761077

申请日：2024-07-01

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Yu-Chiun LIN ,  Po-Nien CHEN ,  Chen Hua TSAI ,  Chih-Yung LIN

IPC: H01L21/3205 ,  H01L21/8238 ,  H01L23/522 ,  H01L27/02 ,  H01L27/06 ,  H01L27/092 ,  H01L29/10 ,  H01L29/66 ,  H01L29/78 ,  H01L21/8234

CPC classification number: H01L28/24 ,  H01L21/32051 ,  H01L21/823821 ,  H01L23/5228 ,  H01L27/0207 ,  H01L27/0629 ,  H01L27/0924 ,  H01L29/1079 ,  H01L29/1095 ,  H01L29/6681 ,  H01L29/785 ,  H01L21/823431 ,  H01L21/823493 ,  H01L29/66545 ,  H01L29/7851

Abstract: A semiconductor device includes a substrate having a first conductivity type, a first well formed in the substrate and having a second conductivity type, a first diffusion region formed in the first well and having the first conductivity type, a first interlayer dielectric layer disposed over the first well and the first diffusion region, and a resistor wire formed of a conductive material and embedded in the first interlayer dielectric layer. The resistor wire overlaps the first diffusion region and at least partially overlaps the first well in plan view.

公开(公告)号：US20240347394A1

公开(公告)日：2024-10-17

申请号：US18757060

申请日：2024-06-27

Applicant: Intel Corporation

Inventor： Srijit MUKHERJEE ,  Christopher J. WIEGAND ,  Tyler J. WEEKS ,  Mark Y. LIU ,  Michael L. HATTENDORF

IPC: H01L21/8238 ,  H01L21/28 ,  H01L21/8234 ,  H01L27/088 ,  H01L27/092 ,  H01L29/49 ,  H01L29/66 ,  H10B10/00

CPC classification number: H01L21/82385 ,  H01L21/28008 ,  H01L21/823431 ,  H01L21/823456 ,  H01L21/823821 ,  H01L27/088 ,  H01L27/0886 ,  H01L27/0924 ,  H01L29/495 ,  H01L29/66477 ,  H10B10/12

Abstract: Integrated circuits including MOSFETs with selectively recessed gate electrodes. Transistors having recessed gate electrodes with reduced capacitive coupling area to adjacent source and drain contact metallization are provided alongside transistors with gate electrodes that are non-recessed and have greater z-height. In embodiments, analog circuits employ transistors with gate electrodes of a given z-height while logic gates employ transistors with recessed gate electrodes of lesser z-height. In embodiments, subsets of substantially planar gate electrodes are selectively etched back to differentiate a height of the gate electrode based on a given transistor's application within a circuit.

公开(公告)号：US20240339537A1

公开(公告)日：2024-10-10

申请号：US18744888

申请日：2024-06-17

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Mark van Dal ,  Martin Christopher Holland ,  Matthias Passlack

IPC: H01L29/78 ,  H01L27/092 ,  H01L29/06 ,  H01L29/10 ,  H01L29/16 ,  H01L29/66 ,  H10B12/00

CPC classification number: H01L29/785 ,  H01L27/0924 ,  H01L29/0673 ,  H01L29/1054 ,  H01L29/1606 ,  H01L29/66795 ,  H10B12/36

Abstract: A semiconductor device includes a fin protruding upwardly from a substrate. The fin includes a first sidewall and an opposing second sidewall and a top surface extending between the first and second sidewalls. The semiconductor device also includes a two-dimensional material layer disposed on the first and second sidewalls of the fin without being disposed on the top surface of the fin, and a gate stack disposed on the fin. The gate stack contacts a channel region defined in the two-dimensional material layer. The two-dimensional material layer includes a flat portion extending laterally away from the fin.

公开(公告)号：US12112989B2

公开(公告)日：2024-10-08

申请号：US17815085

申请日：2022-07-26

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shih-Hao Lin ,  Tzu-Hsiang Hsu ,  Chong-De Lien ,  Szu-Chi Yang ,  Hsin-Wen Su ,  Chih-Hsiang Huang

IPC: H01L21/8238 ,  H01L21/306 ,  H01L27/092 ,  H01L29/423 ,  H01L29/66 ,  H01L29/78 ,  H10B10/00

CPC classification number: H01L21/823814 ,  H01L21/30604 ,  H01L21/823821 ,  H01L27/0924 ,  H01L29/42392 ,  H01L29/6656 ,  H01L29/7848 ,  H10B10/12

Abstract: Semiconductor device and the manufacturing method thereof are disclosed herein. An exemplary method comprises forming first and second semiconductor fins in first and second regions of a substrate, respectively; forming first and second dummy gate stacks over the first and second semiconductor fins, respectively, and forming a spacer layer over the first and the second dummy gate stacks; forming a first pattern layer with a thickness along the spacer layer in the first region; form a first source/drain (S/D) trench along the first pattern layer and epitaxially growing a first epitaxial feature therein; removing the first pattern layer to expose the spacer layer; forming a second pattern layer with a different thickness along the spacer layer in the second region; form a second S/D trench along the second pattern layer and epitaxially growing a second epitaxial feature therein; and removing the second pattern layer to expose the spacer layer.

公开(公告)号：US20240332393A1

公开(公告)日：2024-10-03

申请号：US18741963

申请日：2024-06-13

Applicant: Taiwan Semiconductor Manufacturing Company, LTD.

Inventor： Hsu-Kai CHANG ,  Jhih-Rong HUANG ,  Yen-Tien TUNG ,  Chia-Hung CHU ,  Shuen-Shin LIANG ,  Tzer-Min SHEN ,  Pinyen LIN ,  Sung-Li WANG

IPC: H01L29/45 ,  H01L21/285 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/08 ,  H01L29/417 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L29/45 ,  H01L21/28518 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/823871 ,  H01L27/0924 ,  H01L29/0847 ,  H01L29/41791 ,  H01L29/66795 ,  H01L29/7851

Abstract: A semiconductor device with different configurations of contact structures and a method of fabricating the same are disclosed. The semiconductor device includes first and second gate structures disposed on first and second fin structures, first and second source/drain (S/D) regions disposed on the first and second fin structures, first and second contact structures disposed on the first and second S/D regions, and a dipole layer disposed at an interface between the first nWFM silicide layer and the first S/D region. The first contact structure includes a first nWFM silicide layer disposed on the first S/D region and a first contact plug disposed on the first nWFM silicide layer. The second contact structure includes a pWFM silicide layer disposed on the second S/D region, a second nWFM silicide layer disposed on the pWFM silicide layer, and a second contact plug disposed on the pWFM silicide layer.