公开(公告)号：US20240362391A1

公开(公告)日：2024-10-31

申请号：US18769148

申请日：2024-07-10

Applicant: Intel Corporation

Inventor： Ranjith KUMAR ,  Quan SHI ,  Mark T. BOHR ,  Andrew W. YEOH ,  Sourav CHAKRAVARTY ,  Barbara A. CHAPPELL ,  M. Clair WEBB

IPC: G06F30/392 ,  G06F30/20 ,  G06F30/337 ,  G06F30/347 ,  G06F30/373 ,  G06F30/3947 ,  H01L27/02 ,  H01L27/092 ,  H01L27/118

CPC classification number: G06F30/392 ,  G06F30/337 ,  G06F30/347 ,  H01L27/0207 ,  H01L27/0924 ,  H01L27/11807 ,  G06F30/20 ,  G06F30/373 ,  G06F30/3947 ,  H01L2027/11875

Abstract: Multi version library cell handling and integrated circuit structures fabricated therefrom are described. In an example, an integrated circuit structure includes a plurality of gate lines parallel along a first direction of a substrate and having a pitch along a second direction orthogonal to the first direction. A first version of a cell type is over a first portion of the plurality of gate lines, the first version of the cell type including a first plurality of interconnect lines having a second pitch along the second direction, the second pitch less than the first pitch.

公开(公告)号：US12132041B2

公开(公告)日：2024-10-29

申请号：US17338355

申请日：2021-06-03

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Jacklyn Chang ,  Derek C. Tao ,  Kuo-Yuan Hsu

IPC: H01L27/02 ,  H01L29/66 ,  H01L29/78 ,  H10B99/00

CPC classification number: H01L27/0207 ,  H01L29/66795 ,  H01L29/785 ,  H10B99/00 ,  H01L2029/7858

Abstract: A method, includes: in a strap cell disposed between a memory cell and a logic cell, arranging a first gate across an active region; arranging a second gate next to and in parallel with the first gate and at an end of the active region; and when at least one conductive segment has a first length, arranging the at least one conductive segment across the first gate, the second gate, and no dummy gate in the strap cell. A semiconductor device is also disclosed herein.

公开(公告)号：US12131999B2

公开(公告)日：2024-10-29

申请号：US18512527

申请日：2023-11-17

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jungho Do ,  Sanghoon Baek

IPC: H01L23/528 ,  H01L27/02 ,  H01L27/092 ,  H01L29/423 ,  H01L29/786

CPC classification number: H01L23/5286 ,  H01L27/0207 ,  H01L27/092 ,  H01L29/42392 ,  H01L29/78696

Abstract: A semiconductor device includes a substrate having an active region, a first group of standard cells arranged in a first row on the active region of the substrate and having a first height defined in a column direction, a second group of standard cells arranged in a second row on the active region of the substrate, and having a second height, and a plurality of power lines extending in a row direction and respectively extending along boundaries of the first and the second groups of standard cells. The first and second groups of standard cells each further include a plurality of wiring lines extending in the row direction and arranged in the column direction, and at least some of wiring lines in at least one standard cell of the first and second groups of standard cells are arranged at different spacings and/or pitches.

公开(公告)号：US20240357788A1

公开(公告)日：2024-10-24

申请号：US18756363

申请日：2024-06-27

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Hidehiro FUJIWARA ,  Chih-Yu LIN ,  Hsien-Yu PAN ,  Yasutoshi OKUNO ,  Yen-Huei CHEN ,  Hung-Jen LIAO

IPC: H10B10/00 ,  G06F30/392 ,  H01L23/522 ,  H01L23/528 ,  H01L27/02

CPC classification number: H10B10/12 ,  G06F30/392 ,  H01L23/5226 ,  H01L23/5286 ,  H01L27/0207

Abstract: A memory circuit includes a first pull down transistor, a first pass gate transistor coupled to the first pull down transistor, a second pull down transistor, a second pass gate transistor and a first metal contact. The second pull down transistor has a first active region located on a first level. The second pass gate transistor has a second active region located on the first level, and being coupled to the second pull down transistor. The first metal contact extends from the first active region to the second active region, being located on a second level, and electrically coupling a drain of the second pull down transistor to a drain of the second pass gate transistor. The first pass gate transistor, the second pass gate transistor, the first pull down transistor and the second pull down transistor are part of a four transistor (4T) memory cell.

公开(公告)号：US20240355813A1

公开(公告)日：2024-10-24

申请号：US18761750

申请日：2024-07-02

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Wen-Tzu CHEN ,  Szu-Ping TUNG ,  Guan-Yao TU ,  Hsiang-Ku SHEN ,  Chen-Chiu HUANG ,  Dian-Hau CHEN

IPC: H01L27/06 ,  H01L21/762 ,  H01L27/02 ,  H01L29/06

CPC classification number: H01L27/0629 ,  H01L21/762 ,  H01L27/0207 ,  H01L29/0649

Abstract: A semiconductor device includes a transistor structure disposed over a substrate, a first interlayer dielectric (ILD) layer disposed over the transistor structure, a second ILD layer disposed over the first ILD layer, and a first resistor wire disposed on the second ILD layer, and a second resistor wire disposed on the second ILD layer. A sheet resistance of the first resistor wire is different from a sheet resistance of the second resistor wire.

公开(公告)号：US12125792B2

公开(公告)日：2024-10-22

申请号：US18128742

申请日：2023-03-30

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Jung-Chan Yang ,  Chi-Yu Lu ,  Hui-Zhong Zhuang ,  Chih-Liang Chen

IPC: H01L23/535 ,  H01L21/768 ,  H01L21/8234 ,  H01L23/522 ,  H01L23/528 ,  H01L23/538 ,  H01L27/02 ,  H01L29/40 ,  H01L29/417

CPC classification number: H01L23/535 ,  H01L21/76895 ,  H01L21/823475 ,  H01L23/5221 ,  H01L23/528 ,  H01L23/5286 ,  H01L23/5386 ,  H01L27/0207 ,  H01L29/401 ,  H01L29/41725

Abstract: A method of forming a semiconductor device, includes forming an active region; forming first, second and third metal-to-drain/source (MD) contact structures which extend in a first direction, and correspondingly overlap and electrically couple to the active region; forming a via-to-via (V2V) rail which extends in a second direction perpendicular to the first direction, overlaps at least the first MD contact structure and the third MD contact structures; forming a first via-to-MD (VD) structure over, and electrically coupled to, the first MD contact structure and the V2V rail; and forming a first conductive segment which overlaps the V2V rail, is in a first metallization layer, and is electrically coupled to the first VD structure.

公开(公告)号：US12125787B2

公开(公告)日：2024-10-22

申请号：US17037569

申请日：2020-09-29

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jae-Boong Lee ,  Jung-Ho Do ,  Tae-Joong Song ,  Seung-Young Lee ,  Jong-Hoon Jung ,  Ji-Su Yu

IPC: H01L23/528 ,  G06F30/327 ,  G06F30/392 ,  G06F30/394 ,  H01L21/8234 ,  H01L23/522 ,  H01L27/02 ,  H01L27/088 ,  H01L27/092 ,  H01L27/118 ,  G06F115/02

CPC classification number: H01L23/5286 ,  G06F30/327 ,  G06F30/392 ,  G06F30/394 ,  H01L21/823475 ,  H01L23/5226 ,  H01L23/5283 ,  H01L27/0207 ,  H01L27/11807 ,  G06F2115/02 ,  H01L27/088 ,  H01L27/092 ,  H01L2027/11881

Abstract: An integrated circuit including: a power rail including first and second conductive lines spaced apart from each other in a vertical direction, wherein the first and second conductive lines extend in parallel to each other in a first horizontal direction, and are electrically connected to each other, to supply power to a first standard cell, wherein the first and second conductive lines are disposed at a boundary of the first standard cell; and a third conductive line between the first and second conductive lines and extending in a second horizontal direction orthogonal to the first horizontal direction, to transfer an input signal or an output signal of the first standard cell.

公开(公告)号：US12125737B1

公开(公告)日：2024-10-22

申请号：US18736423

申请日：2024-06-06

Applicant: Monolithic 3D Inc.

Inventor： Zvi Or-Bach ,  Brian Cronquist ,  Deepak C. Sekar

IPC: H01L21/683 ,  G11C8/16 ,  H01L21/74 ,  H01L21/762 ,  H01L21/768 ,  H01L21/822 ,  H01L21/8238 ,  H01L21/84 ,  H01L23/48 ,  H01L23/525 ,  H01L27/02 ,  H01L27/06 ,  H01L27/092 ,  H01L27/10 ,  H01L27/105 ,  H01L27/118 ,  H01L27/12 ,  H01L29/423 ,  H01L29/66 ,  H01L29/78 ,  H01L29/788 ,  H01L29/792 ,  H10B10/00 ,  H10B12/00 ,  H10B20/00 ,  H10B41/20 ,  H10B41/40 ,  H10B41/41 ,  H10B43/20 ,  H10B43/40 ,  H01L23/00 ,  H01L23/367 ,  H01L25/00 ,  H01L25/065 ,  H10B20/20

CPC classification number: H01L21/6835 ,  G11C8/16 ,  H01L21/743 ,  H01L21/76254 ,  H01L21/76898 ,  H01L21/8221 ,  H01L21/823828 ,  H01L21/84 ,  H01L23/481 ,  H01L23/5252 ,  H01L27/0207 ,  H01L27/0688 ,  H01L27/092 ,  H01L27/10 ,  H01L27/105 ,  H01L27/11807 ,  H01L27/11898 ,  H01L27/1203 ,  H01L29/4236 ,  H01L29/66272 ,  H01L29/66621 ,  H01L29/66825 ,  H01L29/66833 ,  H01L29/66901 ,  H01L29/78 ,  H01L29/7841 ,  H01L29/7843 ,  H01L29/7881 ,  H01L29/792 ,  H10B10/00 ,  H10B10/125 ,  H10B12/053 ,  H10B12/09 ,  H10B12/20 ,  H10B12/50 ,  H10B20/00 ,  H10B41/20 ,  H10B41/40 ,  H10B41/41 ,  H10B43/20 ,  H10B43/40 ,  H01L23/3677 ,  H01L24/13 ,  H01L24/16 ,  H01L24/45 ,  H01L24/48 ,  H01L25/0655 ,  H01L25/0657 ,  H01L25/50 ,  H01L27/1214 ,  H01L27/1266 ,  H01L2221/68368 ,  H01L2223/5442 ,  H01L2223/54426 ,  H01L2224/131 ,  H01L2224/16145 ,  H01L2224/16146 ,  H01L2224/16227 ,  H01L2224/16235 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/45124 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/73265 ,  H01L2224/81005 ,  H01L2224/83894 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2924/00011 ,  H01L2924/01002 ,  H01L2924/01004 ,  H01L2924/01013 ,  H01L2924/01018 ,  H01L2924/01019 ,  H01L2924/01029 ,  H01L2924/01046 ,  H01L2924/01066 ,  H01L2924/01068 ,  H01L2924/01077 ,  H01L2924/01078 ,  H01L2924/01322 ,  H01L2924/10253 ,  H01L2924/10329 ,  H01L2924/12032 ,  H01L2924/12033 ,  H01L2924/12036 ,  H01L2924/12042 ,  H01L2924/1301 ,  H01L2924/1305 ,  H01L2924/13062 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/1461 ,  H01L2924/15311 ,  H01L2924/1579 ,  H01L2924/16152 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/30105 ,  H01L2924/3011 ,  H01L2924/3025 ,  H10B12/05 ,  H10B20/20

Abstract: A 3D semiconductor device, the device including: a first level including a first single crystal layer, the first level including first transistors, where each of the first transistors includes a single crystal channel; a first metal layer; a second metal layer overlaying the first metal layer; a second level including second transistors, first memory cells including at least one second transistor, and overlaying the second metal layer, a third level including third transistors and overlaying the second level, a fourth level including fourth transistors, second memory cells including at least one fourth transistor, and overlaying the third level, where the first level includes memory control circuits which control writing to the second memory cells, and at least one Phase-Lock-Loop (“PLL”) circuit or at least one Digital-Lock-Loop (“DLL”) circuit.

公开(公告)号：US20240347525A1

公开(公告)日：2024-10-17

申请号：US18604217

申请日：2024-03-13

Applicant: Micron Technology, Inc.

Inventor： Takamitsu Onda ,  Tomohiro Kitano

IPC: H01L27/02 ,  H01L23/522 ,  H01L27/092

CPC classification number: H01L27/0207 ,  H01L23/5228 ,  H01L27/092

Abstract: According to one or more embodiments of the disclosure, an apparatus comprises: a semiconductor substrate including a first region, a second region, and a third region between the first region and the second region; and a plurality of wiring layers, at least in part, above the third region. The first region includes first transistors of first conductivity-type. The second region includes second transistors of second conductivity-type. The wiring layers include a lower wiring layer, a middle wiring layer, and an upper wiring layer. One or more wirings in the middle wiring layer elongate through the third region in a first direction to connect ones of sources and drains of the first transistors and corresponding ones of sources and drains of the second transistors. One or more wirings in the lower wiring layer elongate in the third region in a second direction perpendicular to the first direction to connect ones of the wirings of the middle wiring layer and corresponding ones of the wirings of the middle wiring layer.

公开(公告)号：US20240347481A1

公开(公告)日：2024-10-17

申请号：US18753409

申请日：2024-06-25

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Julien DELALLEAU ,  Christian RIVERO

IPC: H01L23/00 ,  H01L21/3205 ,  H01L21/3213 ,  H01L21/8234 ,  H01L23/528 ,  H01L27/02 ,  H01L27/088 ,  H01L29/06 ,  H01L29/08 ,  H01L29/10 ,  H01L29/45 ,  H01L29/49

CPC classification number: H01L23/573 ,  H01L21/32053 ,  H01L21/32133 ,  H01L21/823437 ,  H01L21/823475 ,  H01L21/823481 ,  H01L23/528 ,  H01L27/0207 ,  H01L27/088 ,  H01L29/0649 ,  H01L29/0847 ,  H01L29/1079 ,  H01L29/45 ,  H01L29/4916

Abstract: An integrated circuit includes a substrate, an interconnection part, and an isolating region located between the substrate and the interconnection part. A decoy structure is located within the isolating region and includes a silicided sector which is electrically isolated from the substrate.