公开(公告)号：US20230197651A1

公开(公告)日：2023-06-22

申请号：US17557588

申请日：2021-12-21

Applicant: Micron Technology, Inc.

Inventor： Ken Ota ,  Saaya Izumi ,  Tomohiro Kitano

IPC: H01L23/00 ,  H01L25/065

CPC classification number: H01L24/06 ,  H01L25/0657 ,  H01L2224/06177 ,  H01L2225/06562 ,  H01L2225/0651

Abstract: Microelectronic devices may include first bond pads located proximate to, and distributed along, a first side of the microelectronic device. Other bond pads may be located proximate to, and distributed along, another side of the microelectronic device perpendicular to the first side. A first pitch of the first bond pads may be greater than another pitch of the other bond pads. When microelectronic devices are placed side by side, the bond pads on sides of the microelectronic devices proximate to one another may be interposed between one another in the direction parallel to the first shortest distance between adjacent first bond pads.

公开(公告)号：US20200212008A1

公开(公告)日：2020-07-02

申请号：US16235645

申请日：2018-12-28

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Tomohiro Kitano

IPC: H01L25/065 ,  H01L21/66 ,  H01L23/48 ,  H01L23/532 ,  H01L23/00 ,  H01L21/768 ,  H01L25/00

Abstract: A semiconductor device may include a bond pad/probe pad pair that includes a bond pad and a probe pad positioned to be adjacent to each other to form an L shape. The device may also include a through-silicon via (TSV) pad positioned to be at least partially or entirely inside the recess area of the L shape. The bond pad and the probe pad may each have an opening, and at least a portion of the opening of the bond pad may extend into a portion of the opening of the probe pad. The arrangement of the bond pad, the probe pad and the TSV may be implemented in a wafer-on-wafer (WOW) that includes multiple stacked wafers. A method of fabricating the TSV may include etching the stacked wafers to form a TSV opening that extends through the multiple wafers, and filling the TSV opening with conductive material.

公开(公告)号：US20240347525A1

公开(公告)日：2024-10-17

申请号：US18604217

申请日：2024-03-13

Applicant: Micron Technology, Inc.

Inventor： Takamitsu Onda ,  Tomohiro Kitano

IPC: H01L27/02 ,  H01L23/522 ,  H01L27/092

CPC classification number: H01L27/0207 ,  H01L23/5228 ,  H01L27/092

Abstract: According to one or more embodiments of the disclosure, an apparatus comprises: a semiconductor substrate including a first region, a second region, and a third region between the first region and the second region; and a plurality of wiring layers, at least in part, above the third region. The first region includes first transistors of first conductivity-type. The second region includes second transistors of second conductivity-type. The wiring layers include a lower wiring layer, a middle wiring layer, and an upper wiring layer. One or more wirings in the middle wiring layer elongate through the third region in a first direction to connect ones of sources and drains of the first transistors and corresponding ones of sources and drains of the second transistors. One or more wirings in the lower wiring layer elongate in the third region in a second direction perpendicular to the first direction to connect ones of the wirings of the middle wiring layer and corresponding ones of the wirings of the middle wiring layer.

公开(公告)号：US11081467B2

公开(公告)日：2021-08-03

申请号：US16235645

申请日：2018-12-28

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Tomohiro Kitano

IPC: H01L25/065 ,  H01L21/66 ,  H01L23/48 ,  H01L23/532 ,  H01L23/00 ,  H01L21/768 ,  H01L25/00

Abstract: A semiconductor device may include a bond pad/probe pad pair that includes a bond pad and a probe pad positioned to be adjacent to each other to form an L shape. The device may also include a through-silicon via (TSV) pad positioned to be at least partially or entirely inside the recess area of the L shape. The bond pad and the probe pad may each have an opening, and at least a portion of the opening of the bond pad may extend into a portion of the opening of the probe pad. The arrangement of the bond pad, the probe pad and the TSV may be implemented in a wafer-on-wafer (WOW) that includes multiple stacked wafers. A method of fabricating the TSV may include etching the stacked wafers to form a TSV opening that extends through the multiple wafers, and filling the TSV opening with conductive material.

公开(公告)号：US20240379599A1

公开(公告)日：2024-11-14

申请号：US18781853

申请日：2024-07-23

Applicant: Micron Technology, Inc.

Inventor： Ken Ota ,  Saaya Izumi ,  Tomohiro Kitano

IPC: H01L23/00 ,  H01L25/065

Abstract: Stacks of microelectronic devices may include first bond pads located proximate to, and distributed along, a first side of a first microelectronic device. Other bond pads may be located proximate to, and distributed along, another side of the first microelectronic device perpendicular to the first side. A first pitch of the first bond pads may be greater than another pitch of the other bond pads. When the first microelectronic device is supported on a second microelectronic device, the bond pads on opposing sides of the microelectronic devices may be interposed between one another in the direction parallel to the first shortest distance between adjacent first bond pads.

公开(公告)号：US12087716B2

公开(公告)日：2024-09-10

申请号：US17557588

申请日：2021-12-21

Applicant: Micron Technology, Inc.

Inventor： Ken Ota ,  Saaya Izumi ,  Tomohiro Kitano

IPC: H01L23/00 ,  H01L25/065

CPC classification number: H01L24/06 ,  H01L25/0657 ,  H01L2224/06177 ,  H01L2225/0651 ,  H01L2225/06562

Abstract: Microelectronic devices may include first bond pads located proximate to, and distributed along, a first side of the microelectronic device. Other bond pads may be located proximate to, and distributed along, another side of the microelectronic device perpendicular to the first side. A first pitch of the first bond pads may be greater than another pitch of the other bond pads. When microelectronic devices are placed side by side, the bond pads on sides of the microelectronic devices proximate to one another may be interposed between one another in the direction parallel to the first shortest distance between adjacent first bond pads.