公开(公告)号：US20240363393A1

公开(公告)日：2024-10-31

申请号：US18768436

申请日：2024-07-10

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Lei-Chun Chou ,  Chih-Liang Chen ,  Jiann-Tyng Tzeng ,  Chih-Ming Lai ,  Ru-Gun Liu ,  Charles Chew-Yuen Young

IPC分类号： H01L21/74 ,  H01L21/308 ,  H01L21/311 ,  H01L21/3115 ,  H01L21/762 ,  H01L23/535 ,  H01L29/66 ,  H01L29/78 ,  H10B10/00

CPC分类号： H01L21/743 ,  H01L23/535 ,  H01L29/66795 ,  H01L21/3081 ,  H01L21/3086 ,  H01L21/31111 ,  H01L21/31155 ,  H01L21/76224 ,  H01L29/785 ,  H10B10/12

摘要： A semiconductor device includes a buried metal line disposed in a semiconductor substrate, a first dielectric material on a first sidewall of the buried metal line and a second dielectric material on a second sidewall of the buried metal line, a first multiple fins disposed proximate the first sidewall of the buried metal line, a second multiple fins disposed proximate the second sidewall of the buried metal line, a first metal gate structure over the first multiple fins and over the buried metal line, wherein the first metal gate structure extends through the first dielectric material to contact the buried metal line, and a second metal gate structure over the second multiple fins and over the buried metal line.

公开(公告)号：US12125737B1

公开(公告)日：2024-10-22

申请号：US18736423

申请日：2024-06-06

申请人： Monolithic 3D Inc.

发明人： Zvi Or-Bach ,  Brian Cronquist ,  Deepak C. Sekar

IPC分类号： H01L21/683 ,  G11C8/16 ,  H01L21/74 ,  H01L21/762 ,  H01L21/768 ,  H01L21/822 ,  H01L21/8238 ,  H01L21/84 ,  H01L23/48 ,  H01L23/525 ,  H01L27/02 ,  H01L27/06 ,  H01L27/092 ,  H01L27/10 ,  H01L27/105 ,  H01L27/118 ,  H01L27/12 ,  H01L29/423 ,  H01L29/66 ,  H01L29/78 ,  H01L29/788 ,  H01L29/792 ,  H10B10/00 ,  H10B12/00 ,  H10B20/00 ,  H10B41/20 ,  H10B41/40 ,  H10B41/41 ,  H10B43/20 ,  H10B43/40 ,  H01L23/00 ,  H01L23/367 ,  H01L25/00 ,  H01L25/065 ,  H10B20/20

CPC分类号： H01L21/6835 ,  G11C8/16 ,  H01L21/743 ,  H01L21/76254 ,  H01L21/76898 ,  H01L21/8221 ,  H01L21/823828 ,  H01L21/84 ,  H01L23/481 ,  H01L23/5252 ,  H01L27/0207 ,  H01L27/0688 ,  H01L27/092 ,  H01L27/10 ,  H01L27/105 ,  H01L27/11807 ,  H01L27/11898 ,  H01L27/1203 ,  H01L29/4236 ,  H01L29/66272 ,  H01L29/66621 ,  H01L29/66825 ,  H01L29/66833 ,  H01L29/66901 ,  H01L29/78 ,  H01L29/7841 ,  H01L29/7843 ,  H01L29/7881 ,  H01L29/792 ,  H10B10/00 ,  H10B10/125 ,  H10B12/053 ,  H10B12/09 ,  H10B12/20 ,  H10B12/50 ,  H10B20/00 ,  H10B41/20 ,  H10B41/40 ,  H10B41/41 ,  H10B43/20 ,  H10B43/40 ,  H01L23/3677 ,  H01L24/13 ,  H01L24/16 ,  H01L24/45 ,  H01L24/48 ,  H01L25/0655 ,  H01L25/0657 ,  H01L25/50 ,  H01L27/1214 ,  H01L27/1266 ,  H01L2221/68368 ,  H01L2223/5442 ,  H01L2223/54426 ,  H01L2224/131 ,  H01L2224/16145 ,  H01L2224/16146 ,  H01L2224/16227 ,  H01L2224/16235 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/45124 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/73265 ,  H01L2224/81005 ,  H01L2224/83894 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2924/00011 ,  H01L2924/01002 ,  H01L2924/01004 ,  H01L2924/01013 ,  H01L2924/01018 ,  H01L2924/01019 ,  H01L2924/01029 ,  H01L2924/01046 ,  H01L2924/01066 ,  H01L2924/01068 ,  H01L2924/01077 ,  H01L2924/01078 ,  H01L2924/01322 ,  H01L2924/10253 ,  H01L2924/10329 ,  H01L2924/12032 ,  H01L2924/12033 ,  H01L2924/12036 ,  H01L2924/12042 ,  H01L2924/1301 ,  H01L2924/1305 ,  H01L2924/13062 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/1461 ,  H01L2924/15311 ,  H01L2924/1579 ,  H01L2924/16152 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/30105 ,  H01L2924/3011 ,  H01L2924/3025 ,  H10B12/05 ,  H10B20/20

摘要： A 3D semiconductor device, the device including: a first level including a first single crystal layer, the first level including first transistors, where each of the first transistors includes a single crystal channel; a first metal layer; a second metal layer overlaying the first metal layer; a second level including second transistors, first memory cells including at least one second transistor, and overlaying the second metal layer, a third level including third transistors and overlaying the second level, a fourth level including fourth transistors, second memory cells including at least one fourth transistor, and overlaying the third level, where the first level includes memory control circuits which control writing to the second memory cells, and at least one Phase-Lock-Loop (“PLL”) circuit or at least one Digital-Lock-Loop (“DLL”) circuit.

公开(公告)号：US12119309B2

公开(公告)日：2024-10-15

申请号：US17683725

申请日：2022-03-01

申请人： OpenLight Photonics, Inc.

发明人： Avi Feshali ,  John Hutchinson

IPC分类号： H01L23/00 ,  H01L21/02 ,  H01L21/306 ,  H01L21/74 ,  H01L27/12 ,  H01L29/06 ,  H01L29/20

CPC分类号： H01L23/564 ,  H01L21/02164 ,  H01L21/306 ,  H01L21/746 ,  H01L27/1203 ,  H01L29/0649 ,  H01L29/20

摘要： When III-V semiconductor material is bonded to an oxide material, water molecules can degrade the bonding if they become trapped at the interface between the III-V material and the oxide material. Because water molecules can diffuse readily through oxide material, and may not diffuse as readily through III-V material or through silicon, forcing the III-V material against the oxide material can force water molecules at the interface into the oxide material and away from the interface. Water molecules present at the interface can be forced during manufacturing through vertical channels in a silicon layer into a buried oxide layer thereby to enhance bonding between the III-V material and the oxide material. Water molecules can be also forced through lateral channels in the oxide material, past a periphery of the III-V material, and, through diffusion, out of the oxide material into the atmosphere.

公开(公告)号：US12080630B2

公开(公告)日：2024-09-03

申请号：US18534433

申请日：2023-12-08

申请人： Monolithic 3D Inc.

发明人： Zvi Or-Bach ,  Deepak C. Sekar ,  Brian Cronquist

IPC分类号： H01L23/48 ,  H01L21/74 ,  H01L23/34 ,  H01L23/50 ,  H01L23/544 ,  H01L27/02 ,  H01L27/06 ,  H01L27/088 ,  H01L27/118 ,  H01L29/10 ,  H01L29/66 ,  H01L29/732 ,  H01L29/78 ,  H01L29/808 ,  H10B12/00 ,  H10B41/20 ,  H10B41/40 ,  H10B43/20 ,  H10B43/40 ,  H10B63/00

CPC分类号： H01L23/481 ,  H01L21/743 ,  H01L23/34 ,  H01L23/50 ,  H01L23/544 ,  H01L27/0207 ,  H01L27/0688 ,  H01L27/088 ,  H01L27/0886 ,  H01L27/11807 ,  H01L29/1066 ,  H01L29/66272 ,  H01L29/66704 ,  H01L29/66825 ,  H01L29/66901 ,  H01L29/732 ,  H01L29/7841 ,  H01L29/808 ,  H10B12/09 ,  H10B12/20 ,  H10B12/50 ,  H10B41/20 ,  H10B41/40 ,  H10B43/20 ,  H10B43/40 ,  H01L27/0623 ,  H01L2224/16225 ,  H01L2224/73253 ,  H01L2924/12032 ,  H01L2924/1305 ,  H01L2924/13062 ,  H01L2924/13091 ,  H01L2924/1461 ,  H01L2924/16152 ,  H10B63/30 ,  H10B63/845

摘要： A 3D semiconductor device including: a first level including a plurality of first metal layers; a second level overlays the first level and includes at least one single crystal silicon layer, where the second level includes a plurality of transistors and a plurality of second metal layers, each transistor of the plurality of transistors includes a single crystal channel, where the plurality of second metal layers include interconnections between transistors of the plurality of transistors, where the second level is overlaid by a first isolation layer; a connective path from the plurality of transistors to the plurality of first metal layers, where the connective path includes a via disposed through at least the single crystal silicon layer, where each of at least one of the plurality of transistors includes a two sided gate, and where the single crystal silicon layer thickness is less than two microns.

公开(公告)号：US12051674B2

公开(公告)日：2024-07-30

申请号：US18604695

申请日：2024-03-14

申请人： Monolithic 3D Inc.

发明人： Zvi Or-Bach ,  Brian Cronquist

IPC分类号： H01L27/10 ,  H01L21/74 ,  H01L21/768 ,  H01L23/00 ,  H01L23/48 ,  H01L23/485 ,  H01L23/522 ,  H01L25/00 ,  H01L25/065 ,  H01L27/06 ,  H01L27/088 ,  H01L29/66 ,  H01L27/092 ,  H01L29/423 ,  H01L29/78

CPC分类号： H01L25/0657 ,  H01L21/743 ,  H01L21/76898 ,  H01L23/481 ,  H01L23/485 ,  H01L23/522 ,  H01L24/25 ,  H01L25/50 ,  H01L27/0688 ,  H01L27/088 ,  H01L29/66621 ,  H01L27/092 ,  H01L29/4236 ,  H01L29/78 ,  H01L2224/24146 ,  H01L2225/06544 ,  H01L2225/06589 ,  H01L2924/0002 ,  H01L2924/01104 ,  H01L2924/12032 ,  H01L2924/12042 ,  H01L2924/13091 ,  H01L2924/2064 ,  H01L2924/351

摘要： A 3D semiconductor device including: a first level with first transistors, single crystal layer overlaid by at least one first metal layer which includes interconnects between the first transistors forming first control circuits; the first metal layer(s) overlaid by a second metal layer which is overlaid by a second level which includes first memory cells which include second transistors, overlaid by a third level which includes second memory cells which include third transistors and are partially disposed over the control circuits, which control data written to second memory cells; and a fourth metal layer overlaying a third metal layer which overlays the third level; where third transistor gate locations are aligned to second transistor gate locations within less than 100 nm, and the average thickness of fourth metal layer is at least twice the average thickness of second metal layer; the fourth metal layer includes a global power distribution grid.

公开(公告)号：US20240248071A1

公开(公告)日：2024-07-25

申请号：US18414733

申请日：2024-01-17

申请人： Infineon Technologies AG

发明人： Julia Isabel PEREZ BARRAZA ,  Marten OLDSEN ,  Matthias EBERL

IPC分类号： G01N33/00 ,  H01L21/74 ,  H01L21/768 ,  H01L23/00 ,  H01L23/498

CPC分类号： G01N33/005 ,  H01L21/743 ,  H01L21/76871 ,  H01L23/49838 ,  H01L23/49872 ,  H01L24/32 ,  H01L2224/32188

摘要： Examples disclose a sensor for measuring a gas property, in particular a gas composition, more particularly a hydrogen level, wherein the sensor includes a semiconductor die, wherein the semiconductor die includes a measuring cavity, wherein a measuring sensor element is arranged in the measuring cavity, wherein the semiconductor die includes a contact pad, wherein the semiconductor die includes a buried conductor, wherein the buried conductor electrically connects the measuring sensor element to the contact pad, wherein a conductive bonding layer of the semiconductor die surrounds the measuring cavity for providing a conductive bonding surface, and wherein the buried conductor is insulated from the conductive bonding layer. Further examples, disclose methods for manufacturing a sensor.

公开(公告)号：US20240243129A1

公开(公告)日：2024-07-18

申请号：US18622142

申请日：2024-03-29

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Chien Yao Huang ,  Yu-Ti Su

IPC分类号： H01L27/092 ,  H01L21/761 ,  H01L21/8238 ,  H01L29/10 ,  H01L21/74 ,  H01L29/78

CPC分类号： H01L27/0921 ,  H01L21/761 ,  H01L21/823892 ,  H01L29/1083 ,  H01L21/74 ,  H01L29/78

摘要： The present disclosure describes a metal-oxide-semiconductor field-effect transistor (MOSFET) device. The MOSFET device includes a first-type substrate, a deep-second-type well in the first-type substrate, a first-type well over the deep-second-type well, and a second-type well over the deep-second-type well. The second-type well and the deep-second-type well form an enclosed space that includes the first-type well. The MOSFET also includes an embedded semiconductor region (ESR) in a vicinity of the enclosed space. The ESR includes a dopant concentration lower than at least one of a dopant concentration of the first-type well, a dopant concentration of the second-type well, and a dopant concentration of the deep-second-type well.

公开(公告)号：US20240222333A1

公开(公告)日：2024-07-04

申请号：US18604695

申请日：2024-03-14

申请人： Monolithic 3D Inc.

发明人： Zvi Or-Bach ,  Brian Cronquist

IPC分类号： H01L25/065 ,  H01L21/74 ,  H01L21/768 ,  H01L23/00 ,  H01L23/48 ,  H01L23/485 ,  H01L23/522 ,  H01L25/00 ,  H01L27/06 ,  H01L27/088 ,  H01L27/092 ,  H01L29/423 ,  H01L29/66 ,  H01L29/78

CPC分类号： H01L25/0657 ,  H01L21/743 ,  H01L21/76898 ,  H01L23/481 ,  H01L23/485 ,  H01L23/522 ,  H01L24/25 ,  H01L25/50 ,  H01L27/0688 ,  H01L27/088 ,  H01L29/66621 ,  H01L27/092 ,  H01L29/4236 ,  H01L29/78 ,  H01L2224/24146 ,  H01L2225/06544 ,  H01L2225/06589 ,  H01L2924/0002 ,  H01L2924/01104 ,  H01L2924/12032 ,  H01L2924/12042 ,  H01L2924/13091 ,  H01L2924/2064 ,  H01L2924/351

摘要： A 3D semiconductor device including: a first level with first transistors, single crystal layer overlaid by at least one first metal layer which includes interconnects between the first transistors forming first control circuits; the first metal layer(s) overlaid by a second metal layer which is overlaid by a second level which includes first memory cells which include second transistors, overlaid by a third level which includes second memory cells which include third transistors and are partially disposed over the control circuits, which control data written to second memory cells; and a fourth metal layer overlaying a third metal layer which overlays the third level; where third transistor gate locations are aligned to second transistor gate locations within less than 100 nm, and the average thickness of fourth metal layer is at least twice the average thickness of second metal layer; the fourth metal layer includes a global power distribution grid.

公开(公告)号：US20240203793A1

公开(公告)日：2024-06-20

申请号：US18141313

申请日：2023-04-28

申请人： Samsung Electronics Co., Ltd.

发明人： Tae Sun Kim ,  Wonhyuk Hong ,  Jongjin Lee ,  Buhyun Ham ,  Kang-ill Seo

IPC分类号： H01L21/768 ,  H01L21/74

CPC分类号： H01L21/76897 ,  H01L21/74 ,  H01L21/76834 ,  H01L21/76885

摘要： In order to achieve higher contact quality for backside power distribution networks, provided is a backside contact to a semiconductor device having a positive slope and a dielectric sidewall liner, and methods for making the same.

公开(公告)号：US20240120420A1

公开(公告)日：2024-04-11

申请号：US17960245

申请日：2022-10-05

申请人： GlobalFoundries Dresden Module One Limited Liability Company & Co. KG

发明人： Stefan Dünkel ,  Dominik Martin Kleimaier ,  Zhixing Zhao ,  Halid Mulaosmanovic

IPC分类号： H01L29/78 ,  H01L21/74 ,  H01L29/10 ,  H01L29/51 ,  H01L29/66

CPC分类号： H01L29/78391 ,  H01L21/74 ,  H01L29/1083 ,  H01L29/516 ,  H01L29/6684

摘要： Structures including a ferroelectric field-effect transistor and methods of forming a structure including a ferroelectric field-effect transistor. The structure comprises a semiconductor substrate, a semiconductor layer, a dielectric layer arranged between the semiconductor layer and the semiconductor substrate, and first and second wells in the semiconductor substrate. The first well has a first conductivity type, and the second well has a second conductivity type opposite to the first conductivity type. A ferroelectric field-effect transistor comprises a gate structure on the semiconductor layer over the first well and the second well. The gate structure includes a ferroelectric layer comprising a ferroelectric material.