知搜-全球专利检索

  1. Login
  2. Sign Up

Search Results

203 records (took 0.023 seconds)

    MEMORY DEVICE USING SEMICONDUCTOR ELEMENT
    1.
    发明公开
    MEMORY DEVICE USING SEMICONDUCTOR ELEMENT 审中-公开

    公开(公告)号：US20240349482A1

    公开(公告)日：2024-10-17

    申请号：US18624515

    申请日：2024-04-02

    Applicant: Unisantis Electronics Singapore Pte. Ltd.

    Inventor： Masakazu KAKUMU ,  Koji SAKUI ,  Nozomu HARADA

    IPC: H10B12/00 ,  G11C11/404 ,  G11C11/4096

    CPC classification number: H10B12/20 ,  G11C11/404 ,  G11C11/4096

    Abstract: Provided is a memory semiconductor device including an access transistor, in which an n-type semiconductor layer is formed on a p-type semiconductor region provided on a substrate; a first p-type semiconductor layer that has a columnar shape exists in a vertical direction from a portion of the n-type semiconductor layer; an insulating layer that covers a portion of the first p-type semiconductor layer and a portion of the n-type semiconductor layer exists; in contact therewith, a first gate insulating layer contacts the first p-type semiconductor layer; in contact with the first gate insulating layer, a first gate conductive layer exists; a second p-type semiconductor layer whose surface is recessed exists on the first p-type semiconductor layer; a second gate insulating layer and a second gate conductive layer exist thereabove; and an n+ layer is provided on both sides thereof.

    Memory device through use of semiconductor device
    3.
    发明授权
    Memory device through use of semiconductor device 有权

    公开(公告)号：US12108589B2

    公开(公告)日：2024-10-01

    申请号：US17741914

    申请日：2022-05-11

    Applicant: Unisantis Electronics Singapore Pte. Ltd.

    Inventor： Koji Sakui ,  Nozomu Harada

    IPC: G11C11/40 ,  G11C11/404 ,  G11C11/4096 ,  H10B12/00

    CPC classification number: H10B12/20 ,  G11C11/404 ,  G11C11/4096

    Abstract: A memory device includes pages, each being composed of a plurality of memory cells arrayed on a substrate in row form. The memory device controls voltages to be applied to a first gate conductor layer, a second gate conductor layer, a first impurity region, and a second impurity region of each of the memory cells included in the pages to perform a page write operation of holding a hole group formed by an impact ionization phenomenon or a gate induced drain leakage current in a channel semiconductor layer, and controls voltages to be applied to the first gate conductor layer, the second gate conductor layer, the third gate conductor layer, the fourth gate conductor layer, the first impurity region, and the second impurity region to perform a page erase operation of removing the hole group out of the channel semiconductor layer. The first impurity layer of each of the memory cells is connected to a source line, the second impurity region is connected to a bit line, one of the first gate conductor layer and the second gate conductor layer is connected to a word line, and the other is connected to a first driving control line. The bit line is connected to a sense amplifier circuit via a switching circuit. When in a page read operation, the memory device reads page data in a memory cell group selected by the word line to the bit line, and performs charge sharing between the bit line and a charge sharing node of the switching circuit opposite to the bit line to accelerate a read determination by the sense amplifier circuit.

    Memory and method for manufacturing same
    4.
    发明授权
    Memory and method for manufacturing same 有权

    公开(公告)号：US12108588B2

    公开(公告)日：2024-10-01

    申请号：US17479201

    申请日：2021-09-20

    Applicant: CHANGXIN MEMORY TECHNOLOGIES, INC.

    Inventor： Kui Zhang

    IPC: H10B12/00 ,  H01L29/66 ,  H01L29/78

    CPC classification number: H10B12/20 ,  H01L29/66666 ,  H01L29/7827 ,  H01L29/7841

    Abstract: A memory and a method for manufacturing the same are provided. The memory includes a substrate; at least one pair of transistors on a surface of the substrate, in which conductive channels of the transistors extend in a direction perpendicular to the surface of the substrate; storage layers, which each are located, in the direction perpendicular to the surface of the substrate, on a side surface of each of the transistors, the storage layers are interconnected with the conductive channels of the transistors, any one of the storage layers is located between the pair of transistors, and the storage layers are configured to store electric charges and transfer the electric charges between the storage layers and the conductive channels interconnected therewith.

    Method for manufacturing semiconductor element-including memory device
    5.
    发明授权
    Method for manufacturing semiconductor element-including memory device 有权

    公开(公告)号：US12106796B2

    公开(公告)日：2024-10-01

    申请号：US17994922

    申请日：2022-11-28

    Applicant: Unisantis Electronics Singapore Pte. Ltd.

    Inventor： Nozomu Harada ,  Koji Sakui

    IPC: G11C5/06 ,  G11C11/409 ,  H10B12/00

    CPC classification number: G11C11/409 ,  G11C5/06 ,  H10B12/20 ,  H10B12/50

    Abstract: An N+ layer 11a and N+ layers 13a to 13d that are disposed on both ends of Si pillars 12a to 12d standing on a substrate 10 in a vertical direction, a TiN layer 18a that surrounds a gate HfO2 layer 17a surrounding the Si pillars 12a to 12d and that extends between the Si pillars 12a and 12b, a TiN layer 18b that surrounds the gate HfO2 layer 17a and that extends between the Si pillars 12c and 12d, a TiN layer 26a that surrounds a gate HfO2 layer 17b surrounding the Si pillars 12a to 12d and that extends between the Si pillars 12a and 12b, and a TiN layer 26b that surrounds the gate HfO2 layer 17b and that extends between the Si pillars 12c and 12d are formed. Voltages applied to the N+ layers 11a and 13a to 13d and the TiN layers 18a, 18b, 26a, and 26b are controlled to perform a data write operation of retaining, inside the Si pillars 12a to 12d, a group of positive holes generated by an impact ionization phenomenon and a data erase operation of discharging the group of positive holes from the inside of the Si pillars 12a to 12d.

    MEMORY DEVICE USING SEMICONDUCTOR ELEMENT
    6.
    发明公开
    MEMORY DEVICE USING SEMICONDUCTOR ELEMENT 审中-公开

    公开(公告)号：US20240321342A1

    公开(公告)日：2024-09-26

    申请号：US18609167

    申请日：2024-03-19

    Applicant: Unisantis Electronics Singapore Pte. Ltd.

    Inventor： Masakazu KAKUMU ,  Koji Sakui ,  Nozomu Harada

    IPC: G11C11/4096 ,  H01L23/528 ,  H10B12/00

    CPC classification number: G11C11/4096 ,  H01L23/5283 ,  H10B12/20

    Abstract: A memory device includes a first n-layer formed on a first p-layer on a substrate; a second n-layer extending vertically with a second p-layer placed thereon; a first insulating layer partially covering the n-layers; a first gate insulating layer in contact with the first insulating layer; a first gate conductor layer in contact with the gate insulating layer and first insulating layer; a second insulating layer in contact with the first gate conductor layer; and a MOSFET formed of a third p-layer placed on the second p-layer, a second gate insulating layer placed atop the third p-layer, n+ layers placed on opposite ends of the third p-layer, and a second gate conductor layer. Contact area between the second p-layer and second n-layer is smaller than a cross-section of the second p-layer. A write/erase operation is performed by applying voltages to the n+ layers, gate conductor layers, and first n-layer.

    MEMORY DEVICE USING SEMICONDUCTOR ELEMENT
    9.
    发明公开
    MEMORY DEVICE USING SEMICONDUCTOR ELEMENT 审中-公开

    公开(公告)号：US20240206151A1

    公开(公告)日：2024-06-20

    申请号：US18545216

    申请日：2023-12-19

    Applicant: Unisantis Electronics Singapore Pte. Ltd.

    Inventor： Koji SAKUI ,  Masakazu KAKUMU ,  Nozomu HARADA

    IPC: H10B12/00 ,  G11C11/404 ,  G11C11/4096

    CPC classification number: H10B12/20 ,  G11C11/404 ,  G11C11/4096

    Abstract: A memory device includes at least one memory array made up of pages and bit lines. Each page includes multiple memory cells connected to a bit line. A plate line is connected to a first gate conductor layer, a source line is connected to an n+ layer, the bit line is connected to an n+ layer, and a word line is connected to a second gate conductor layer. A write operation of holding positive hole groups near a gate insulating layer and an erase operation of removing the positive hole groups are performed by controlling voltages applied to the source line, the bit line, the word line, the plate line, and the bottom line, where the positive hole groups are generated in a channel region of a third semiconductor layer by a gate induced drain leakage current.

    SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF
    10.
    发明公开
    SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF 审中-公开

    公开(公告)号：US20240206149A1

    公开(公告)日：2024-06-20

    申请号：US18541791

    申请日：2023-12-15

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Minjun Lee ,  Hyoseok Kim ,  Yongseok Kim

    IPC: H10B12/00

    CPC classification number: H10B12/20

    Abstract: A semiconductor device includes a source line extending in a first horizontal direction on a substrate, a channel layer extending in a vertical direction perpendicular to an upper surface of the substrate, and including a first end, a second end opposite to the first end, and a channel layer sidewall connecting the first end with the second end, the first end being disposed on the source line, a trap layer disposed on the channel layer sidewall, a gate insulating layer disposed on an outer surface of the trap layer, a word line disposed on at least one sidewall of the gate insulating layer and extending in a second horizontal direction crossing the first horizontal direction, a drain area disposed on the second end of the channel layer and including a metal or metal nitride, and a bit line disposed on the drain area and extending in the first horizontal direction.

Patent Agency Ranking