公开(公告)号：US12113130B2

公开(公告)日：2024-10-08

申请号：US18195480

申请日：2023-05-10

Applicant: Micron Technology, Inc.

Inventor： Hung-Wei Liu ,  Sameer Chhajed ,  Jeffery B. Hull ,  Anish A Khandekar

IPC: H01L29/78 ,  H01L21/02 ,  H01L29/04 ,  H01L29/66 ,  H10B12/00

CPC classification number: H01L29/7841 ,  H01L21/02686 ,  H01L29/04 ,  H01L29/66666 ,  H01L29/7827 ,  H10B12/20

Abstract: A transistor comprises a top source/drain region, a bottom source/drain region, a channel region vertically between the top and bottom source/drain regions, and a gate operatively laterally-adjacent the channel region. At least one of the top source/drain region, the bottom source/drain region, and the channel region are crystalline. All crystal grains within the at least one of the top source/drain region, the bottom source/drain region, and the channel region have average crystal sizes within 0.064 μm3 of one another. Other embodiments, including methods, are disclosed.