公开(公告)号：US12237227B2

公开(公告)日：2025-02-25

申请号：US17654408

申请日：2022-03-11

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Kai-Qiang Wen ,  Shih-Fen Huang ,  Shih-Chun Fu ,  Chi-Yuan Shih ,  Feng Yuan

IPC: H01L21/8234 ,  H01L27/105 ,  H01L29/78 ,  H01L49/02

Abstract: A device includes a fin on a substrate; a first transistor, including: a drain region and a first source region in the fin; and a first gate structure on the fin between the first source region and the drain region; a second transistor, including: the drain region and a second source region in the fin; and a second gate structure on the fin between the second source region and the drain region; a first resistor, including: the first source region and a first resistor region in the fin; and a third gate structure on the fin between the first source region and the first resistor region; and a second resistor, including: the second source region and a second resistor region in the fin; and a fourth gate structure on the fin between the second source region and the second resistor region.

公开(公告)号：US12156397B2

公开(公告)日：2024-11-26

申请号：US17737295

申请日：2022-05-05

Applicant: Zeno Semiconductor, Inc.

Inventor： Yuniarto Widjaja

IPC: G11C5/02 ,  G11C7/00 ,  G11C8/10 ,  G11C8/16 ,  G11C11/40 ,  G11C11/403 ,  G11C11/405 ,  H01Q1/22 ,  H10B12/00 ,  H10B12/10 ,  H01L27/105

Abstract: Multi-port semiconductor memory cells including a common floating body region configured to be charged to a level indicative of a memory state of the memory cell. The multi-port semiconductor memory cells include a plurality of gates and conductive regions interfacing with said floating body region. Arrays of memory cells and method of operating said memory arrays are disclosed for making a memory device.

公开(公告)号：US12150386B2

公开(公告)日：2024-11-19

申请号：US17820056

申请日：2022-08-16

Applicant: FUJIFILM CORPORATION

Inventor： Keeyoung Park ,  Atsushi Mizutani

IPC: H10N50/01 ,  C23F1/30 ,  C23F1/40 ,  C23F4/00 ,  H01L21/3065 ,  H01L21/308 ,  H01L27/105 ,  H10N50/10

Abstract: A treatment liquid contains orthoperiodic acid and water, and the pH is 11 or more. It is preferable that the content of orthoperiodic acid in the treatment liquid is 0.01% to 5% by mass with respect to the total mass of the treatment liquid.

公开(公告)号：US12148761B2

公开(公告)日：2024-11-19

申请号：US17221896

申请日：2021-04-05

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Atsushi Umezaki

IPC: G09G3/36 ,  G02F1/1333 ,  G02F1/1362 ,  G02F1/1368 ,  G09G3/3266 ,  G11C19/28 ,  H01H71/02 ,  H01H71/10 ,  H01L27/105 ,  H01L27/12 ,  H01L29/786 ,  G02F1/1343 ,  G02F1/1345 ,  H01L27/13 ,  H01L29/423 ,  H10K59/121 ,  H10K59/131

Abstract: By applying an AC pulse to a gate of a transistor which easily deteriorates, a shift in threshold voltage of the transistor is suppressed. However, in a case where amorphous silicon is used for a semiconductor layer of a transistor, the occurrence of a shift in threshold voltage naturally becomes a problem for a transistor which constitutes a part of circuit that generates an AC pulse. A shift in threshold voltage of a transistor which easily deteriorates and a shift in threshold voltage of a turned-on transistor are suppressed by signal input to a gate electrode of the transistor which easily deteriorates through the turned-on transistor. In other words, a structure for applying an AC pulse to a gate electrode of a transistor which easily deteriorates through a transistor to a gate electrode of which a high potential (VDD) is applied, is included.

公开(公告)号：US20240379739A1

公开(公告)日：2024-11-14

申请号：US18783147

申请日：2024-07-24

Applicant: Micron Technology, Inc.

Inventor： Michael Mutch ,  Manuj Nahar ,  Wayne I. Kinney

IPC: H01L29/04 ,  H01L21/02 ,  H01L21/324 ,  H01L27/105 ,  H01L29/161 ,  H01L29/786

Abstract: A device comprises a first crystalline material, a second material in a substantially crystalline form, a blocking material between the first crystalline material and the second material, and a third material in a substantially crystalline form and adjacent the second material. A crystallization temperature of the third material is different from a crystallization temperature of the second material. At least one of the second material and the third material is substantially free of a grain boundary therein. Also disclosed is a device including a transistor. The transistor comprises a first crystalline material, a substantially continuous crystalline structure, and a blocking material between the first crystalline material and the substantially continuous crystalline structure. The substantially continuous crystalline structure comprises a second crystalline material and a third crystalline material having a different crystallization temperature than the second crystalline material. The substantially continuous crystalline structure is substantially free of a grain boundary therein.

公开(公告)号：US12120890B2

公开(公告)日：2024-10-15

申请号：US18344150

申请日：2023-06-29

Applicant: TDK CORPORATION

Inventor： Zhenyao Tang ,  Tomoyuki Sasaki

IPC: H10B99/00 ,  G01R33/09 ,  H01L27/105 ,  H10B61/00 ,  H10N50/10 ,  H10N50/85

CPC classification number: H10B99/00 ,  G01R33/093 ,  G01R33/098 ,  H01L27/105 ,  H10B61/22 ,  H10N50/10 ,  H10N50/85

Abstract: A TMR element includes a magnetic tunnel junction, a side wall portion that covers a side surface of the magnetic tunnel junction, and a minute particle region that is disposed in the side wall portion. The side wall portion includes an insulation material. The minute particle region includes the insulation material and a plurality of minute magnetic metal particles that are dispersed in the insulation material. The minute particle region is electrically connected in parallel with the magnetic tunnel junction.

公开(公告)号：US12100611B2

公开(公告)日：2024-09-24

申请号：US18389577

申请日：2023-11-14

Applicant: Monolithic 3D Inc.

Inventor： Zvi Or-Bach ,  Brian Cronquist ,  Deepak C. Sekar

IPC: H01L21/683 ,  G11C8/16 ,  H01L21/74 ,  H01L21/762 ,  H01L21/768 ,  H01L21/822 ,  H01L21/8238 ,  H01L21/84 ,  H01L23/48 ,  H01L23/525 ,  H01L27/02 ,  H01L27/06 ,  H01L27/092 ,  H01L27/10 ,  H01L27/105 ,  H01L27/118 ,  H01L27/12 ,  H01L29/423 ,  H01L29/66 ,  H01L29/78 ,  H01L29/788 ,  H01L29/792 ,  H10B10/00 ,  H10B12/00 ,  H10B20/00 ,  H10B41/20 ,  H10B41/40 ,  H10B41/41 ,  H10B43/20 ,  H10B43/40 ,  H01L23/00 ,  H01L23/367 ,  H01L25/00 ,  H01L25/065 ,  H10B20/20

CPC classification number: H01L21/6835 ,  G11C8/16 ,  H01L21/743 ,  H01L21/76254 ,  H01L21/76898 ,  H01L21/8221 ,  H01L21/823828 ,  H01L21/84 ,  H01L23/481 ,  H01L23/5252 ,  H01L27/0207 ,  H01L27/0688 ,  H01L27/092 ,  H01L27/10 ,  H01L27/105 ,  H01L27/11807 ,  H01L27/11898 ,  H01L27/1203 ,  H01L29/4236 ,  H01L29/66272 ,  H01L29/66621 ,  H01L29/66825 ,  H01L29/66833 ,  H01L29/66901 ,  H01L29/78 ,  H01L29/7841 ,  H01L29/7843 ,  H01L29/7881 ,  H01L29/792 ,  H10B10/00 ,  H10B10/125 ,  H10B12/053 ,  H10B12/09 ,  H10B12/20 ,  H10B12/50 ,  H10B20/00 ,  H10B41/20 ,  H10B41/40 ,  H10B41/41 ,  H10B43/20 ,  H10B43/40 ,  H01L23/3677 ,  H01L24/13 ,  H01L24/16 ,  H01L24/45 ,  H01L24/48 ,  H01L25/0655 ,  H01L25/0657 ,  H01L25/50 ,  H01L27/1214 ,  H01L27/1266 ,  H01L2221/68368 ,  H01L2223/5442 ,  H01L2223/54426 ,  H01L2224/131 ,  H01L2224/16145 ,  H01L2224/16146 ,  H01L2224/16227 ,  H01L2224/16235 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/45124 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/73265 ,  H01L2224/81005 ,  H01L2224/83894 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2924/00011 ,  H01L2924/01002 ,  H01L2924/01004 ,  H01L2924/01013 ,  H01L2924/01018 ,  H01L2924/01019 ,  H01L2924/01029 ,  H01L2924/01046 ,  H01L2924/01066 ,  H01L2924/01068 ,  H01L2924/01077 ,  H01L2924/01078 ,  H01L2924/01322 ,  H01L2924/10253 ,  H01L2924/10329 ,  H01L2924/12032 ,  H01L2924/12033 ,  H01L2924/12036 ,  H01L2924/12042 ,  H01L2924/1301 ,  H01L2924/1305 ,  H01L2924/13062 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/1461 ,  H01L2924/15311 ,  H01L2924/1579 ,  H01L2924/16152 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/30105 ,  H01L2924/3011 ,  H01L2924/3025 ,  H10B12/05 ,  H10B20/20

Abstract: A method for producing 3D semiconductor devices including: providing a first level including first transistors and a first single crystal layer; forming a first metal layer on top of the first level; forming a second metal layer on top of the first metal layer; forming at least one second level on top of or above the second metal layer; performing a lithography step on the second level; forming at least one third level on top of or above the second level; performing processing steps to form first memory cells within the second level and second memory cells within the third level, where the first memory cells include at least one second transistor, the second memory cells include at least one third transistor, second transistors comprise gate electrodes comprising metal, and then forming at least four independent memory arrays which include some first memory cells and/or second memory cells.

公开(公告)号：US12057472B2

公开(公告)日：2024-08-06

申请号：US18050772

申请日：2022-10-28

Applicant: Micron Technology, Inc.

Inventor： Michael Mutch ,  Manuj Nahar ,  Wayne I. Kinney

IPC: H01L29/04 ,  H01L21/02 ,  H01L21/324 ,  H01L29/161 ,  H01L27/105 ,  H01L29/786

CPC classification number: H01L29/04 ,  H01L21/02532 ,  H01L21/02667 ,  H01L21/324 ,  H01L29/161 ,  H01L27/105 ,  H01L29/78642

Abstract: A method includes forming a semiconductor structure. The structure includes a first material, a blocking material, a second material in an amorphous form, and a third material in an amorphous form. The blocking material is disposed between the first material and the second material. At least the second material and the third material each comprise silicon and/or germanium. The structure is exposed to a temperature above a crystallization temperature of the third material and below a crystallization temperature of the second material. Semiconductor structures, memory devices, and systems are also disclosed.

公开(公告)号：US20240234423A9

公开(公告)日：2024-07-11

申请号：US18538009

申请日：2023-12-13

Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

Inventor： Shunpei YAMAZAKI

IPC: H01L27/105 ,  G11C11/405 ,  G11C16/04 ,  H01L21/02 ,  H01L21/46 ,  H01L21/8258 ,  H01L27/12 ,  H01L29/06 ,  H01L29/786 ,  H10B41/10 ,  H10B41/20 ,  H10B41/30 ,  H10B41/35 ,  H10B41/70

CPC classification number: H01L27/105 ,  G11C11/405 ,  G11C16/0433 ,  H01L21/02664 ,  H01L21/46 ,  H01L21/8258 ,  H01L27/1225 ,  H01L29/06 ,  H01L29/7869 ,  H01L29/78693 ,  H10B41/10 ,  H10B41/20 ,  H10B41/30 ,  H10B41/35 ,  H10B41/70 ,  H01L27/0207

Abstract: Disclosed is a semiconductor device capable of functioning as a memory device. The memory device comprises a plurality of memory cells, and each of the memory cells contains a first transistor and a second transistor. The first transistor is provided over a substrate containing a semiconductor material and has a channel formation region in the substrate. The second transistor has an oxide semiconductor layer. The gate electrode of the first transistor and one of the source and drain electrodes of the second transistor are electrically connected to each other. The extremely low off current of the second transistor allows the data stored in the memory cell to be retained for a significantly long time even in the absence of supply of electric power.

公开(公告)号：US12033884B2

公开(公告)日：2024-07-09

申请号：US18542983

申请日：2023-12-18

Applicant: Monolithic 3D Inc.

Inventor： Zvi Or-Bach ,  Brian Cronquist ,  Deepak C. Sekar

IPC: H01L21/74 ,  G11C8/16 ,  H01L21/683 ,  H01L21/762 ,  H01L21/768 ,  H01L21/822 ,  H01L21/8238 ,  H01L21/84 ,  H01L23/48 ,  H01L23/525 ,  H01L27/02 ,  H01L27/06 ,  H01L27/092 ,  H01L27/10 ,  H01L27/105 ,  H01L27/118 ,  H01L27/12 ,  H01L29/423 ,  H01L29/66 ,  H01L29/78 ,  H01L29/788 ,  H01L29/792 ,  H10B10/00 ,  H10B12/00 ,  H10B20/00 ,  H10B41/20 ,  H10B41/40 ,  H10B41/41 ,  H10B43/20 ,  H10B43/40 ,  H01L23/00 ,  H01L23/367 ,  H01L25/00 ,  H01L25/065 ,  H10B20/20

CPC classification number: H01L21/6835 ,  G11C8/16 ,  H01L21/743 ,  H01L21/76254 ,  H01L21/76898 ,  H01L21/8221 ,  H01L21/823828 ,  H01L21/84 ,  H01L23/481 ,  H01L23/5252 ,  H01L27/0207 ,  H01L27/0688 ,  H01L27/092 ,  H01L27/10 ,  H01L27/105 ,  H01L27/11807 ,  H01L27/11898 ,  H01L27/1203 ,  H01L29/4236 ,  H01L29/66272 ,  H01L29/66621 ,  H01L29/66825 ,  H01L29/66833 ,  H01L29/66901 ,  H01L29/78 ,  H01L29/7841 ,  H01L29/7843 ,  H01L29/7881 ,  H01L29/792 ,  H10B10/00 ,  H10B10/125 ,  H10B12/053 ,  H10B12/09 ,  H10B12/20 ,  H10B12/50 ,  H10B20/00 ,  H10B41/20 ,  H10B41/40 ,  H10B41/41 ,  H10B43/20 ,  H10B43/40 ,  H01L23/3677 ,  H01L24/13 ,  H01L24/16 ,  H01L24/45 ,  H01L24/48 ,  H01L25/0655 ,  H01L25/0657 ,  H01L25/50 ,  H01L27/1214 ,  H01L27/1266 ,  H01L2221/68368 ,  H01L2223/5442 ,  H01L2223/54426 ,  H01L2224/131 ,  H01L2224/16145 ,  H01L2224/16146 ,  H01L2224/16227 ,  H01L2224/16235 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/45124 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/73265 ,  H01L2224/81005 ,  H01L2224/83894 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2924/00011 ,  H01L2924/01002 ,  H01L2924/01004 ,  H01L2924/01013 ,  H01L2924/01018 ,  H01L2924/01019 ,  H01L2924/01029 ,  H01L2924/01046 ,  H01L2924/01066 ,  H01L2924/01068 ,  H01L2924/01077 ,  H01L2924/01078 ,  H01L2924/01322 ,  H01L2924/10253 ,  H01L2924/10329 ,  H01L2924/12032 ,  H01L2924/12033 ,  H01L2924/12036 ,  H01L2924/12042 ,  H01L2924/1301 ,  H01L2924/1305 ,  H01L2924/13062 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/1461 ,  H01L2924/15311 ,  H01L2924/1579 ,  H01L2924/16152 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/30105 ,  H01L2924/3011 ,  H01L2924/3025 ,  H10B12/05 ,  H10B20/20

Abstract: A method for producing 3D semiconductor devices including: providing a first level including first transistors and a first single crystal layer; forming a first metal layer on top of the first level; forming a second metal layer on top of the first metal layer; forming at least one (ALO) second level on top of or above the second metal layer; performing a lithography step on the second level; forming ALO third level on top of or above the ALO second level; performing processing steps to form first memory cells within the ALO second level and second memory cells within the ALO third level, first memory cells include ALO second transistor, second memory cells include ALO third transistor, first metal layer thickness is at least 50% greater than the second metal layer thickness, ALO first transistor controls power delivery to ALO second transistor; then dicing using a laser system.