公开(公告)号：US20240355822A1

公开(公告)日：2024-10-24

申请号：US18304393

申请日：2023-04-21

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Che Chi SHIH ,  Tsung-En LEE ,  Wu-Wei TSAI ,  Wei-Yen WOON ,  Szuya LIAO

IPC: H01L27/092 ,  H01L21/02 ,  H01L21/8258 ,  H01L29/06 ,  H01L29/24 ,  H01L29/423 ,  H01L29/66 ,  H01L29/775

CPC classification number: H01L27/0922 ,  H01L21/02565 ,  H01L21/02603 ,  H01L21/8258 ,  H01L29/0673 ,  H01L29/24 ,  H01L29/42392 ,  H01L29/66969 ,  H01L29/775

Abstract: A semiconductor device includes a first transistor and a second transistor vertically stacked over the first transistor. The first transistor includes a semiconductor channel layer, a first gate structure wrapping around the semiconductor channel layer, and first source/drain structures on opposite ends of the semiconductor channel layer. The second transistor includes a metal oxide channel layer, a second gate structure wrapping around the metal oxide channel layer, and second source/drain structures on opposite ends of the metal oxide channel layer.

公开(公告)号：US20240347338A1

公开(公告)日：2024-10-17

申请号：US18755651

申请日：2024-06-26

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Shin-Hung Li

IPC: H01L21/02 ,  H01L21/8258 ,  H01L29/66 ,  H01L29/786

CPC classification number: H01L21/02565 ,  H01L21/8258 ,  H01L29/66969 ,  H01L29/7869

Abstract: The present invention provides a semiconductor structure, including a substrate, a thin-film transistor (TFT) on the substrate, wherein the thin-film transistor including a TFT channel layer, a first source and a first drain in the TFT channel layer and a first capping layer on the TFT channel layer. A MOSFET is on the substrate, with a second gate, a second source and a second drain on two sides of the second gate and a second capping layer on the second gate, wherein top surfaces of the second capping layer and the first capping layer are leveled, and a first ILD layer is on the first capping layer and the second capping layer, wherein the first ILD layer and the first capping layer function collectively as a gate dielectric layer for the TFT.

公开(公告)号：US20240312823A1

公开(公告)日：2024-09-19

申请号：US18371774

申请日：2023-09-22

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Yeongkwon Ko ,  Seunghun Shin ,  Jihun Jung ,  Junyeong Heo

IPC: H01L21/683 ,  H01L21/67 ,  H01L21/8258

CPC classification number: H01L21/6836 ,  H01L21/67092 ,  H01L21/67132 ,  H01L21/8258 ,  H01L2221/68336

Abstract: Provide is a method of splitting a semiconductor chip, the method including performing a back-end-of-line (BEOL) process including forming a plurality of chip areas on a semiconductor substrate, forming a splitting area, which separates the plurality of chip areas, on the semiconductor substrate, and forming a wire on a first surface of the semiconductor substrate, forming a cutout auxiliary layer in the splitting area of the first surface of the semiconductor substrate, and performing mechanical machining by bringing a mechanical machining device into contact with the cutout auxiliary layer, wherein the cutout auxiliary layer is adjacent to the plurality of chip areas.

公开(公告)号：US20240136358A1

公开(公告)日：2024-04-25

申请号：US18538009

申请日：2023-12-13

Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

Inventor： Shunpei YAMAZAKI

IPC: H01L27/105 ,  G11C11/405 ,  G11C16/04 ,  H01L21/02 ,  H01L21/46 ,  H01L21/8258 ,  H01L27/12 ,  H01L29/06 ,  H01L29/786 ,  H10B41/10 ,  H10B41/20 ,  H10B41/30 ,  H10B41/35 ,  H10B41/70

CPC classification number: H01L27/105 ,  G11C11/405 ,  G11C16/0433 ,  H01L21/02664 ,  H01L21/46 ,  H01L21/8258 ,  H01L27/1225 ,  H01L29/06 ,  H01L29/7869 ,  H01L29/78693 ,  H10B41/10 ,  H10B41/20 ,  H10B41/30 ,  H10B41/35 ,  H10B41/70 ,  H01L27/0207

Abstract: Disclosed is a semiconductor device capable of functioning as a memory device. The memory device comprises a plurality of memory cells, and each of the memory cells contains a first transistor and a second transistor. The first transistor is provided over a substrate containing a semiconductor material and has a channel formation region in the substrate. The second transistor has an oxide semiconductor layer. The gate electrode of the first transistor and one of the source and drain electrodes of the second transistor are electrically connected to each other. The extremely low off current of the second transistor allows the data stored in the memory cell to be retained for a significantly long time even in the absence of supply of electric power.

公开(公告)号：US11854909B2

公开(公告)日：2023-12-26

申请号：US17814870

申请日：2022-07-26

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.

Inventor： Man-Ho Kwan ,  Fu-Wei Yao ,  Ru-Yi Su ,  Chun Lin Tsai ,  Alexander Kalnitsky

IPC: H01L21/8252 ,  H01L21/02 ,  H01L21/265 ,  H01L21/768 ,  H01L21/8258 ,  H01L29/06 ,  H01L29/205 ,  H01L23/535 ,  H01L21/761 ,  H01L27/06 ,  H01L29/16 ,  H01L29/778 ,  H01L29/78 ,  H01L29/866 ,  H01L29/20

CPC classification number: H01L21/8252 ,  H01L21/0254 ,  H01L21/02381 ,  H01L21/02543 ,  H01L21/02546 ,  H01L21/02549 ,  H01L21/26546 ,  H01L21/761 ,  H01L21/76898 ,  H01L21/8258 ,  H01L27/0605 ,  H01L27/0688 ,  H01L29/0646 ,  H01L29/16 ,  H01L29/205 ,  H01L23/535 ,  H01L29/2003 ,  H01L29/7786 ,  H01L29/78 ,  H01L29/866

Abstract: A semiconductor structure and method for manufacturing thereof are provided. The semiconductor structure includes a silicon substrate having a first surface, a III-V layer on the first surface of the silicon substrate and over a first active region, and an isolation region in a portion of the III-V layer extended beyond the first active region. The first active region is in proximal to the first surface. The method includes the following operations. A silicon substrate having a first device region and a second device region is provided, a first active region is defined in the first device region, a III-V layer is formed on the silicon substrate, an isolation region is defined across a material interface in the III-V layer by an implantation operation, and an interconnect penetrating through the isolation region is formed.

公开(公告)号：US11843051B2

公开(公告)日：2023-12-12

申请号：US17860820

申请日：2022-07-08

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Mirco Cantoro ,  Yeoncheol Heo

IPC: H01L29/78 ,  H01L29/06 ,  H01L27/088 ,  H01L29/417 ,  H01L29/10 ,  H01L29/66 ,  H01L21/8238 ,  H01L21/8234 ,  H01L21/8258

CPC classification number: H01L29/7849 ,  H01L21/823431 ,  H01L21/823807 ,  H01L21/823821 ,  H01L27/0886 ,  H01L29/0657 ,  H01L29/1054 ,  H01L29/41791 ,  H01L29/66545 ,  H01L29/785 ,  H01L21/8258 ,  H01L21/823481

Abstract: The present disclosure relates to a field-effect transistor and a method of fabricating the same. A field-effect transistor includes a semiconductor substrate including a first semiconductor material having a first lattice constant, and a fin structure on the semiconductor substrate. The fin structure includes a second semiconductor material having a second lattice constant that is different from the first lattice constant. The fin structure further includes a lower portion that is elongated in a first direction, a plurality of upper portions protruding from the lower portion and elongated in a second direction that is different from the first direction, and a gate structure crossing the plurality of upper portions.

公开(公告)号：US11830950B2

公开(公告)日：2023-11-28

申请号：US17346359

申请日：2021-06-14

Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

Inventor： Yasutaka Nakazawa ,  Junichi Koezuka ,  Takashi Hamochi

IPC: H01L29/786 ,  H01L27/146 ,  H01L29/66 ,  H01L27/15 ,  H01L29/45 ,  H01L27/12 ,  H10B12/00 ,  H01L21/768 ,  H01L29/417 ,  H01L27/088 ,  H01L21/8258 ,  H01L27/06

CPC classification number: H01L29/7869 ,  H01L21/76843 ,  H01L21/76856 ,  H01L27/1207 ,  H01L27/1225 ,  H01L27/146 ,  H01L27/15 ,  H01L29/41733 ,  H01L29/45 ,  H01L29/66969 ,  H01L29/78618 ,  H01L29/78648 ,  H01L29/78696 ,  H10B12/312 ,  H01L21/8258 ,  H01L27/0629 ,  H01L27/0688 ,  H01L27/088

Abstract: A semiconductor device including an oxide semiconductor film that includes a transistor with excellent electrical characteristics is provided. It is a semiconductor device including a transistor. The transistor includes a gate electrode, a first insulating film, an oxide semiconductor film, a source electrode, a drain electrode, and a second insulating film. The source electrode and the drain electrode each include a first conductive film, a second conductive film over and in contact with the first conductive film, and a third conductive film over and in contact with the second conductive film. The second conductive film contains copper, the first conductive film and the third conductive film include a material that inhibits diffusion of copper, and an end portion of the second conductive film includes a region containing copper and silicon.

公开(公告)号：US11830880B2

公开(公告)日：2023-11-28

申请号：US16691730

申请日：2019-11-22

Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

Inventor： Shunpei Yamazaki

IPC: H01L27/105 ,  H01L29/06 ,  H01L29/786 ,  H01L21/02 ,  H01L21/46 ,  H01L27/12 ,  G11C11/405 ,  G11C16/04 ,  H01L21/8258 ,  H10B41/10 ,  H10B41/20 ,  H10B41/30 ,  H10B41/35 ,  H10B41/70 ,  H01L29/78 ,  H01L49/02 ,  H01L27/02

CPC classification number: H01L27/105 ,  G11C11/405 ,  G11C16/0433 ,  H01L21/02664 ,  H01L21/46 ,  H01L21/8258 ,  H01L27/1225 ,  H01L29/06 ,  H01L29/7869 ,  H01L29/78693 ,  H10B41/10 ,  H10B41/20 ,  H10B41/30 ,  H10B41/35 ,  H10B41/70 ,  H01L27/0207 ,  H01L28/60 ,  H01L29/7833

Abstract: Disclosed is a semiconductor device capable of functioning as a memory device. The memory device comprises a plurality of memory cells, and each of the memory cells contains a first transistor and a second transistor. The first transistor is provided over a substrate containing a semiconductor material and has a channel formation region in the substrate. The second transistor has an oxide semiconductor layer. The gate electrode of the first transistor and one of the source and drain electrodes of the second transistor are electrically connected to each other. The extremely low off current of the second transistor allows the data stored in the memory cell to be retained for a significantly long time even in the absence of supply of electric power.

公开(公告)号：US11817450B2

公开(公告)日：2023-11-14

申请号：US17181613

申请日：2021-02-22

Applicant: MACOM Technology Solutions Holdings, Inc.

Inventor： Timothy E. Boles ,  Wayne Mack Struble

IPC: H01L27/06 ,  H01L21/762 ,  H01L27/12 ,  H01L21/02 ,  H01L21/8258

CPC classification number: H01L27/0605 ,  H01L21/02389 ,  H01L21/76264 ,  H01L21/8258 ,  H01L27/0629 ,  H01L27/1207

Abstract: Apparatus and methods relating to heterolithic microwave integrated circuits HMICs are described. An HMIC can include different semiconductor devices formed from different semiconductor systems in different regions of a same substrate. An HMIC can also include bulk regions of low-loss electrically-insulating material extending through the substrate and located between the different semiconductor regions. Passive RF circuit elements can be formed on the low-loss electrically-insulating material.

公开(公告)号：US20230317716A1

公开(公告)日：2023-10-05

申请号：US18024296

申请日：2021-08-26

Applicant: ROHM CO., LTD.

Inventor： Yuya TAMURA

IPC: H01L27/06 ,  H01L29/16 ,  H01L29/20 ,  H01L29/778 ,  H01L29/861 ,  H01L29/872 ,  H01L29/66 ,  H01L21/8258

CPC classification number: H01L27/0629 ,  H01L29/16 ,  H01L29/2003 ,  H01L29/7786 ,  H01L29/8613 ,  H01L29/872 ,  H01L29/66136 ,  H01L29/66462 ,  H01L21/8258

Abstract: A semiconductor device includes an electron transit layer formed on first principal surface of the semiconductor layer, an electron supply layer formed on the electron transit layer, a gate conductive layer formed on the electron supply layer, a source conductive layer and a drain conductive layer that are formed on the electron supply layer such that the gate conductive layer is interposed between the source conductive layer and the drain conductive layer, an anode conductive layer that is formed on second principal surface of the semiconductor layer and that is electrically connected to the source conductive layer, a cathode conductive layer that is formed on the first principal surface of the semiconductor layer and that is electrically connected to the drain conductive layer, and a rectifying element formed by a part of the semiconductor layer such that the rectifying element is electrically connected to the anode and cathode conductive layers.