公开(公告)号：US12125847B2

公开(公告)日：2024-10-22

申请号：US17618897

申请日：2021-11-12

申请人： INNOSCIENCE (SUZHOU) TECHNOLOGY CO., LTD.

发明人： Qingyuan He ,  Ronghui Hao ,  Fu Chen ,  Jinhan Zhang ,  King Yuen Wong

IPC分类号： H01L27/085 ,  H01L21/8252 ,  H01L23/522

CPC分类号： H01L27/085 ,  H01L21/8252 ,  H01L23/5221

摘要： A nitride-based semiconductor device includes a first nitride-based semiconductor layer, a second nitride-based semiconductor layer, a first nitride-based transistor, and a second nitride-based transistor. The first nitride-based transistor applies the 2DEG region as a channel thereof and comprising a first drain electrode that makes contact with the second nitride-based semiconductor layer to form a first Schottky diode with the second nitride-based semiconductor layer. The second nitride-based transistor applies the 2DEG region as a channel thereof and includes a second drain electrode that makes contact with the second nitride-based semiconductor layer to form a second Schottky diode with the second nitride-based semiconductor layer, such that the first Schottky diode and the second Schottky diode are connected to the same node.

公开(公告)号：US20240274599A1

公开(公告)日：2024-08-15

申请号：US18629823

申请日：2024-04-08

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Chan-Hong CHERN

IPC分类号： H01L27/088 ,  H01L21/8252 ,  H01L29/43 ,  H01L29/66 ,  H01L29/778 ,  H03K17/687

CPC分类号： H01L27/0883 ,  H01L21/8252 ,  H01L29/432 ,  H01L29/66462 ,  H01L29/7786 ,  H03K17/6871

摘要： Apparatus and circuits including transistors with different threshold voltages and methods of fabricating the same are disclosed. In one example, a semiconductor structure is disclosed. The semiconductor structure includes: a substrate; an active layer that is formed over the substrate and comprises a plurality of active portions; a polarization modulation layer comprising a plurality of polarization modulation portions each of which is disposed on a corresponding one of the plurality of active portions; and a plurality of transistors each of which comprises a source region, a drain region, and a gate structure formed on a corresponding one of the plurality of polarization modulation portions. The transistors have at least three different threshold voltages.

公开(公告)号：US12009205B2

公开(公告)日：2024-06-11

申请号：US17835596

申请日：2022-06-08

申请人： QROMIS, Inc.

发明人： Vladimir Odnoblyudov ,  Cem Basceri ,  Shari Farrens

IPC分类号： H01L21/02 ,  C23C16/24 ,  C23C16/30 ,  C23C16/34 ,  C30B25/18 ,  C30B29/06 ,  C30B29/40 ,  C30B29/68 ,  C30B33/06 ,  C30B33/08 ,  H01L21/74 ,  H01L21/8252 ,  H01L23/535 ,  H01L29/20 ,  H01L21/762 ,  H01L29/778 ,  H01L29/80

CPC分类号： H01L21/0242 ,  C23C16/24 ,  C23C16/303 ,  C23C16/345 ,  C30B25/18 ,  C30B29/06 ,  C30B29/406 ,  C30B29/68 ,  C30B33/06 ,  C30B33/08 ,  H01L21/02428 ,  H01L21/0245 ,  H01L21/02488 ,  H01L21/02491 ,  H01L21/02505 ,  H01L21/02532 ,  H01L21/0254 ,  H01L21/743 ,  H01L21/8252 ,  H01L23/535 ,  H01L29/2003 ,  H01L21/76254 ,  H01L29/7783 ,  H01L29/802

摘要： A substrate including a support structure. The support structure including a polycrystalline ceramic core and a first adhesion layer coupled to the polycrystalline ceramic core. The support structure further including a conductive layer coupled to the first adhesion layer, a second adhesion layer coupled to the conductive layer, and a barrier layer coupled to the second adhesion layer. The substrate further including a bonding layer coupled to the support structure. The substrate further including a substantially single crystal layer comprising at least one of silicon carbide, sapphire, or gallium nitride coupled to the bonding layer. The substrate further including an epitaxial semiconductor layer coupled to the substantially single crystal layer.

公开(公告)号：US11973078B2

公开(公告)日：2024-04-30

申请号：US18104734

申请日：2023-02-01

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Chan-Hong Chern

IPC分类号： H01L27/088 ,  H01L21/8252 ,  H01L29/43 ,  H01L29/66 ,  H01L29/778 ,  H03K17/687

CPC分类号： H01L27/0883 ,  H01L21/8252 ,  H01L29/432 ,  H01L29/66462 ,  H01L29/7786 ,  H03K17/6871

摘要： Apparatus and circuits including transistors with different threshold voltages and methods of fabricating the same are disclosed. In one example, a semiconductor structure is disclosed. The semiconductor structure includes: a substrate; an active layer that is formed over the substrate and comprises a plurality of active portions; a polarization modulation layer comprising a plurality of polarization modulation portions each of which is disposed on a corresponding one of the plurality of active portions; and a plurality of transistors each of which comprises a source region, a drain region, and a gate structure formed on a corresponding one of the plurality of polarization modulation portions. The transistors have at least three different threshold voltages.

公开(公告)号：US11929364B2

公开(公告)日：2024-03-12

申请号：US17479543

申请日：2021-09-20

申请人： MACOM Technology Solutions Holdings, Inc.

发明人： Gabriel R. Cueva ,  Timothy E. Boles ,  Wayne Mack Struble

IPC分类号： H01L27/06 ,  H01L21/02 ,  H01L21/74 ,  H01L21/76 ,  H01L21/762 ,  H01L21/8252 ,  H01L23/528 ,  H01L23/535 ,  H01L23/66 ,  H01L29/06 ,  H01L29/20

CPC分类号： H01L27/0605 ,  H01L21/0254 ,  H01L21/743 ,  H01L21/746 ,  H01L21/7605 ,  H01L21/76202 ,  H01L21/8252 ,  H01L23/5286 ,  H01L23/535 ,  H01L23/66 ,  H01L29/0649 ,  H01L29/2003

摘要： Semiconductor structures with reduced parasitic capacitance between interconnects and ground, for example, are described. In one case, a semiconductor structure includes a substrate and a low dielectric constant material region in the substrate. The low dielectric constant material region is positioned between a first device area in the semiconductor structure and a second device area in the semiconductor structure. The semiconductor structure also includes a III-nitride material layer over the substrate. The III-nitride material layer extends over the substrate in the first device area, over the low dielectric constant material region, and over the substrate in the second device area. The semiconductor structure can also include a first device formed in the III-nitride material layer in the first device area, a second device in the III-nitride material layer in the second device area, and an interconnect formed over the low dielectric constant material region. The interconnect can provide a continuous conductive path of metal from the first device area, over the low dielectric constant material region, and to the second device area.

公开(公告)号：US20240063218A1

公开(公告)日：2024-02-22

申请号：US17618897

申请日：2021-11-12

申请人： INNOSCIENCE (SUZHOU) TECHNOLOGY CO., LTD.

发明人： Qingyuan HE ,  Ronghui HAO ,  Fu CHEN ,  Jinhan ZHANG ,  King Yuen WONG

IPC分类号： H01L27/085 ,  H01L21/8252 ,  H01L23/522

CPC分类号： H01L27/085 ,  H01L21/8252 ,  H01L23/5221

摘要： A nitride-based semiconductor device includes a first nitride-based semiconductor layer, a second nitride-based semiconductor layer, a first nitride-based transistor, and a second nitride-based transistor. The first nitride-based transistor applies the 2DEG region as a channel thereof and comprising a first drain electrode that makes contact with the second nitride-based semiconductor layer to form a first Schottky diode with the second nitride-based semiconductor layer. The second nitride-based transistor applies the 2DEG region as a channel thereof and includes a second drain electrode that makes contact with the second nitride-based semiconductor layer to form a second Schottky diode with the second nitride-based semiconductor layer, such that the first Schottky diode and the second Schottky diode are connected to the same node.

公开(公告)号：US20230420305A1

公开(公告)日：2023-12-28

申请号：US18250348

申请日：2021-09-27

申请人： ROCKLEY PHOTONICS LIMITED

发明人： Ludovic CARO ,  Guomin YU

IPC分类号： H01L21/8252 ,  G02B6/136 ,  H01L21/683 ,  H01L21/78

CPC分类号： H01L21/8252 ,  G02B6/136 ,  H01L21/6835 ,  H01L21/7813 ,  H01L2221/68354

摘要： A coupon wafer for a micro-transfer printing process. The coupon wafer including a device coupon attached to a substrate of the coupon wafer by one or more tethers; wherein the or each tether is a pillar extending at least partially through the device coupon to contact the substrate of the coupon wafer.

公开(公告)号：US20230178367A1

公开(公告)日：2023-06-08

申请号：US18104148

申请日：2023-01-31

申请人： QROMIS, Inc.

发明人： Vladimir Odnoblyudov ,  Cem Basceri ,  Shari Farrens

IPC分类号： H01L21/02 ,  C30B33/08 ,  H01L21/74 ,  H01L21/8252 ,  H01L23/535 ,  H01L29/20 ,  C30B29/06 ,  C30B29/40 ,  C30B29/68 ,  C23C16/24 ,  C23C16/34 ,  C30B25/18 ,  C30B33/06 ,  C23C16/30

CPC分类号： H01L21/0242 ,  C30B33/08 ,  H01L21/0245 ,  H01L21/02532 ,  H01L21/0254 ,  H01L21/743 ,  H01L21/8252 ,  H01L23/535 ,  H01L29/2003 ,  C30B29/06 ,  C30B29/406 ,  C30B29/68 ,  C23C16/24 ,  C23C16/345 ,  H01L21/02428 ,  H01L21/02488 ,  H01L21/02491 ,  H01L21/02505 ,  C30B25/18 ,  C30B33/06 ,  C23C16/303 ,  H01L29/7783

摘要： A substrate includes a support structure comprising a polycrystalline ceramic core, a first adhesion layer encapsulating the polycrystalline ceramic core, a barrier layer encapsulating the first adhesion layer, a second adhesion layer coupled to the barrier layer, and a conductive layer coupled to the second adhesion layer. The substrate also includes a bonding layer coupled to the support structure, a substantially single crystal silicon layer coupled to the bonding layer, and an epitaxial semiconductor layer coupled to the substantially single crystal silicon layer.

公开(公告)号：US11616056B2

公开(公告)日：2023-03-28

申请号：US16649712

申请日：2018-01-18

申请人： INTEL CORPORATION

发明人： Aaron D. Lilak ,  Patrick Morrow ,  Anh Phan ,  Cheng-Ying Huang ,  Rishabh Mehandru ,  Gilbert Dewey ,  Willy Rachmady

IPC分类号： H01L27/06 ,  H01L21/8252 ,  H01L27/092 ,  H01L29/20 ,  H01L29/205 ,  H01L29/66 ,  H01L29/778 ,  H01L29/861

摘要： An integrated circuit structure includes a first semiconductor fin extending horizontally in a length direction and including a bottom portion and a top portion above the bottom portion, a bottom transistor associated with the bottom portion of the first semiconductor fin, a top transistor above the bottom transistor and associated with the top portion of the first semiconductor fin, and a first vertical diode. The first vertical diode includes: a bottom region associated with at least the bottom portion of the first semiconductor fin, the bottom region including one of n-type and p-type dopant; a top region associated with at least the top portion of the first semiconductor fin, the top region including the other of n-type and p-type dopant; a bottom terminal electrically connected to the bottom region; and a top terminal electrically connected to the top region at the top portion of the first semiconductor fin.

公开(公告)号：US20230090106A1

公开(公告)日：2023-03-23

申请号：US17481253

申请日：2021-09-21

申请人： Intel Corporation

发明人： Han Wui THEN ,  Marko RADOSAVLJEVIC ,  Sansaptak DASGUPTA ,  Paul B. FISCHER ,  Walid M. HAFEZ ,  Nicole K. THOMAS ,  Nityan NAIR ,  Pratik KOIRALA ,  Paul NORDEEN ,  Tushar TALUKDAR ,  Thomas HOFF ,  Thoe MICHAELOS

IPC分类号： H01L29/04 ,  H01L27/092 ,  H01L29/778 ,  H01L21/8252 ,  H01L27/12 ,  H01L21/84

摘要： Gallium nitride (GaN) layer transfer for integrated circuit technology is described. In an example, an integrated circuit structure includes a substrate including silicon. A first layer including gallium and nitrogen is over a first region of the substrate, the first layer having a gallium-polar orientation with a top crystal plane consisting of a gallium face. A second layer including gallium and nitrogen is over a second region of the substrate, the second layer having a nitrogen-polar orientation with a top crystal plane consisting of a nitrogen face.