公开(公告)号：US20250072096A1

公开(公告)日：2025-02-27

申请号：US18606375

申请日：2024-03-15

Applicant: Samsung Electronics Co., Ltd.

Inventor： Gi Woong SHIM ,  Seong Heum CHOI ,  Do Sun LEE ,  Hyo Seok CHOI ,  Rak Hwan KIM ,  Chung Hwan SHIN

IPC: H01L21/8234 ,  H01L21/308 ,  H01L21/768 ,  H01L27/088 ,  H01L29/06 ,  H01L29/423 ,  H01L29/66 ,  H01L29/775 ,  H01L29/786

Abstract: A method of fabricating a semiconductor device includes: forming an active pattern on a substrate, forming a source/drain pattern on the active pattern, forming a contact hole on the source/drain pattern, forming a contact barrier layer, which has an upper surface of a first height based on a bottom surface of the contact hole, in the contact hole, forming a passivation layer on the contact barrier layer in the contact hole, forming a mask layer on the passivation layer in the contact hole, removing an upper portion of the contact barrier layer so that an upper surface of the contact barrier layer has a second height lower than the first height, removing the passivation layer and the mask layer, and forming a contact filling layer, which covers the upper surface of the contact barrier layer and fills the contact hole, in the contact hole.

公开(公告)号：US20250072070A1

公开(公告)日：2025-02-27

申请号：US18507039

申请日：2023-11-11

Applicant: Taiwan Semiconductor Manufacturing Company Ltd.

Inventor： Chen An Hsu ,  Chien-Wei Lee ,  Anhao Cheng ,  Yen-Liang Lin ,  Ru-Shang Hsiao ,  Wei-Lun Chung

IPC: H01L29/08 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/66

Abstract: A semiconductor structure includes a substrate and a first epitaxial source/drain feature extending into the semiconductor layer. The semiconductor structure includes a first doped region located in the semiconductor layer below the first epitaxial source/drain feature. The first doped region includes a dopant at a first concentration. The semiconductor structure includes a second epitaxial source/drain feature extending into the semiconductor layer. The semiconductor structure includes a second doped region located in the semiconductor layer below the second epitaxial source/drain feature. The second doped region includes the dopant at a second concentration that is less than the first concentration.

公开(公告)号：US12237393B2

公开(公告)日：2025-02-25

申请号：US17853955

申请日：2022-06-30

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Chung-Ting Ko ,  Bi-Fen Wu ,  Chi-On Chui

IPC: H01L29/49 ,  H01L21/28 ,  H01L21/3215 ,  H01L21/8234 ,  H01L27/088

Abstract: A semiconductor device including a gate structure disposed on a substrate is provided. The gate structure includes a work function setting layer and a work function tuning layer sequentially disposed on substrate. The work function tuning layer is in contact with an interface surface positioned between the work function setting layer and the work function tuning layer, and a material of the interface surface is different from the work function setting layer.

公开(公告)号：US20250063809A1

公开(公告)日：2025-02-20

申请号：US18940119

申请日：2024-11-07

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Wang-Chun Huang ,  Chih-Hao Wang ,  Ching-Wei Tsai ,  Kuan-Lun Cheng

IPC: H01L27/088 ,  H01L21/02 ,  H01L21/306 ,  H01L21/308 ,  H01L21/8234 ,  H01L29/06 ,  H01L29/08 ,  H01L29/423 ,  H01L29/66 ,  H01L29/78 ,  H01L29/786

Abstract: The present disclosure describes a structure including a fin field effect transistor (finFET) and a nano-sheet transistor on a substrate and a method of forming the structure. The method can include forming first and second vertical structures over a substrate, where each of the first and the second vertical structures can include a buffer region and a first channel layer formed over the buffer region. The method can further include disposing a masking layer over the first channel layer of the first and second vertical structures, removing a portion of the first vertical structure to form a first recess, forming a second channel layer in the first recess, forming a second recess in the second channel layer, and disposing an insulating layer in the second recess.

公开(公告)号：US20250063808A1

公开(公告)日：2025-02-20

申请号：US18451137

申请日：2023-08-17

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.

Inventor： KUAN-TING PAN ,  JIA-CHUAN YOU ,  CHIA-HAO CHANG ,  KUO-CHENG CHIANG ,  CHIH-HAO WANG

IPC: H01L27/088 ,  H01L21/8234 ,  H01L29/06 ,  H01L29/423 ,  H01L29/66 ,  H01L29/775

Abstract: A semiconductor structure includes a first dielectric wall over a substrate, and two metal gate structures disposed at two sides of the first dielectric wall. Each of the metal gate structures includes a plurality of nanosheets stacked over the substrate and separated from each other, a high-k gate dielectric layer covering each of the nanosheets, and a metal layer covering and over the plurality of nanosheets and the high-k gate dielectric layer. The high-k gate dielectric layer of each metal gate structure is disposed between the metal layer of each metal gate structure and the first dielectric wall.

公开(公告)号：US20250063792A1

公开(公告)日：2025-02-20

申请号：US18526473

申请日：2023-12-01

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Jia-Chuan YOU ,  Chia-Hao CHANG ,  Chu-Yuan HSU ,  Kuo-Cheng CHIANG ,  Chih-Hao WANG

IPC: H01L29/66 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/06 ,  H01L29/08 ,  H01L29/423 ,  H01L29/775 ,  H01L29/786

Abstract: Gate isolation processes (e.g., gate-to-source/drain contact isolation) are described herein. An exemplary contact gate isolation process may include recessing (e.g., by etching) sidewall portions of a high-k gate dielectric and gate spacers of a gate structure to form a contact gate isolation (CGI) opening that exposes sidewalls of a gate electrode of the gate structure, forming a gate isolation liner along the sidewalls of the gate electrode that partially fills the CGI opening, and forming a gate isolation layer over the gate isolation liner that fills a remainder of the CGI opening. A dielectric constant of the gate isolation liner is less than a dielectric constant of the high-k gate dielectric. A dielectric constant of the gate isolation layer is less than a dielectric constant of the high-k gate dielectric. A dielectric constant of the gate isolation layer may be less than a dielectric constant of the gate isolation layer.

公开(公告)号：US20250062161A1

公开(公告)日：2025-02-20

申请号：US18404345

申请日：2024-01-04

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Chen-Ming Lee

IPC: H01L21/768 ,  H01L21/8238 ,  H01L23/48 ,  H01L27/088

Abstract: In an embodiment, an exemplary method includes forming a source/drain opening extending into a substrate, forming a semiconductor layer in a bottom portion of the source/drain opening, forming a dielectric feature in the source/drain opening and on the semiconductor layer, epitaxially growing a source/drain feature in the source/drain opening, wherein the source/drain feature is in direct contact with the dielectric feature, removing the semiconductor layer and a portion of the substrate disposed directly under the semiconductor layer to form a trench, selectively removing the dielectric feature to enlarge the trench, after the selectively removing of the dielectric feature, forming a silicide layer in the enlarged trench, and depositing a conductive layer in the enlarged trench and in direct contact with the silicide layer.

公开(公告)号：US12230633B2

公开(公告)日：2025-02-18

申请号：US18362764

申请日：2023-07-31

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Jhon-Jhy Liaw

IPC: H01L27/08 ,  H01L21/8234 ,  H01L27/02 ,  H01L27/088 ,  H01L29/06 ,  H01L29/66 ,  H01L27/092 ,  H01L27/12 ,  H01L29/78 ,  H10B12/00

Abstract: An IC structure includes first, second, and third circuits. The first circuit includes a first semiconductor fin, a first gate electrode extending across the first semiconductor fin, and a first gate dielectric layer spacing the first gate electrode apart from the first semiconductor fin. The second circuit includes a second semiconductor fin, a second gate electrode extending across the second semiconductor fin, and a second gate dielectric layer spacing the second gate electrode apart from the second semiconductor fin. The third circuit includes a third semiconductor fin, a third gate electrode extending across the third semiconductor fin, and a third gate dielectric layer spacing the third gate electrode apart from the third semiconductor fin. The first gate dielectric layer has a greater thickness than the second gate dielectric layer. The third semiconductor fin has a smaller width than the second semiconductor fin.

公开(公告)号：US12230631B2

公开(公告)日：2025-02-18

申请号：US18508024

申请日：2023-11-13

Applicant: SKYWORKS SOLUTIONS, INC.

Inventor： Guillaume Alexandre Blin ,  Ambarish Roy ,  Seungwoo Jung

IPC: H01L27/088 ,  H01L21/8234 ,  H01L29/417 ,  H01L29/423 ,  H03K17/10 ,  H03K17/687 ,  H03K17/693 ,  H04B1/00 ,  H04B1/04 ,  H04B1/40 ,  H01L23/538 ,  H01L29/78 ,  H01L29/786

Abstract: Devices and methods for layout-dependent voltage handling improvement in switch stacks. In some embodiments, a switching device can include a first terminal and a second terminal, a radio-frequency signal path implemented between the first terminal and the second terminal, and a plurality of switching elements connected in series to form a stack between the second terminal and ground. The stack can have an orientation relative to the radio-frequency signal path, and the switching elements can have a non-uniform distribution of a first parameter based in part on the orientation of the stack.

公开(公告)号：US12230571B2

公开(公告)日：2025-02-18

申请号：US17576007

申请日：2022-01-14

Applicant: Samsung Electronics Co., Ltd.

Inventor： Gilhwan Son ,  Hoonseok Seo ,  Saehan Park ,  Byounghak Hong ,  Kang-Ill Seo

IPC: H01L23/528 ,  H01L21/74 ,  H01L21/768 ,  H01L21/8234 ,  H01L23/48 ,  H01L23/485 ,  H01L23/535 ,  H01L27/088

Abstract: Methods of forming an integrated circuit devices may include forming a transistor on a first surface of a substrate. The transistor may include an active region, a source/drain region contacting the active region and a gate electrode on the active region. The methods may also include forming a conductive wire that is electrically connected to the source/drain region, forming a trench extending through the substrate by etching a second surface of the substrate, which is opposite the first surface of the substrate, and forming a power rail in the trench. The power rail is electrically connected to conductive wire.