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    LIMITED LATERAL GROWTH OF S/D EPI BY OUTER DIELECTRIC LAYER IN 3-DIMENSIONAL STACKED DEVICE
    4.
    发明公开
    LIMITED LATERAL GROWTH OF S/D EPI BY OUTER DIELECTRIC LAYER IN 3-DIMENSIONAL STACKED DEVICE 审中-公开

    公开(公告)号：US20230335549A1

    公开(公告)日：2023-10-19

    申请号：US17866343

    申请日：2022-07-15

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Inchan Hwang ,  Jaejik Baek ,  Byounghak Hong ,  Saehan Park ,  Kang-ill Seo

    IPC: H01L21/822 ,  H01L29/66 ,  H01L27/06

    CPC classification number: H01L27/0688 ,  H01L21/8221 ,  H01L29/66545 ,  H01L29/6656

    Abstract: An integrated circuit includes a first semiconductor device and a second semiconductor device adjacent to the first semiconductor device. Each of the first and second semiconductor devices includes a lower transistor and an upper transistor on the lower transistor, and the upper and lower transistors each include a source region, a drain region, and a channel region extending between the source region and the drain region. The integrated circuit also includes a first dielectric spacer extending along an inner sidewall of the channel region of the upper and/or lower transistor of the first semiconductor device, a second dielectric spacer facing the first dielectric spacer and extending along an inner sidewall of the channel region of the upper and/or lower transistor of the second semiconductor device. The integrated circuit also includes an interconnect contact between the first semiconductor device and the second semiconductor device.

    CROSS-COUPLED GATE DESIGN FOR STACKED DEVICE WITH SEPARATED TOP-DOWN GATE
    5.
    发明申请
    CROSS-COUPLED GATE DESIGN FOR STACKED DEVICE WITH SEPARATED TOP-DOWN GATE 有权

    公开(公告)号：US20250056873A1

    公开(公告)日：2025-02-13

    申请号：US18930077

    申请日：2024-10-29

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Seunghyun SONG ,  Seungyoung Lee ,  Saehan Park

    IPC: H01L27/092 ,  H01L21/822 ,  H01L21/8238 ,  H01L27/06 ,  H01L29/423 ,  H10B10/00

    Abstract: A semiconductor device and a method of manufacturing the same are provided. The semiconductor device includes a cross-coupled gate circuit in a three-dimensional (3D) stack including a plurality of transistors, a first gate line of a first transistor among the plurality of transistors connected to a fourth gate line of a fourth transistor among the plurality of transistors, a second gate line of a second transistor among the plurality of transistors connected to a third gate line of a third transistor among the plurality of transistors, a first conductor connecting the first gate line and the fourth gate line, a second conductor connecting the second gate line and the third gate line. The first gate line and the second gate line are arranged above the third gate line and the fourth gate line, respectively.

    SELECTIVE DOUBLE DIFFUSION BREAK STRUCTURES FOR MULTI-STACK SEMICONDUCTOR DEVICE
    7.
    发明申请
    SELECTIVE DOUBLE DIFFUSION BREAK STRUCTURES FOR MULTI-STACK SEMICONDUCTOR DEVICE 有权

    公开(公告)号：US20220336473A1

    公开(公告)日：2022-10-20

    申请号：US17382060

    申请日：2021-07-21

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Byounghak Hong ,  Seunghyun Song ,  Saehan Park ,  Seungyoung Lee ,  Inchan Hwang

    IPC: H01L27/11 ,  H01L29/06 ,  H01L29/423 ,  H01L29/66 ,  H01L29/786 ,  H01L21/762

    Abstract: A multi-stack semiconductor device includes: a plurality of lower transistor structures arranged on a lower stack and including a plurality of lower fin structures surrounded by a plurality of lower gate structures, respectively; a plurality of upper transistor structures arranged on an upper stack and including a plurality of upper fin structures surrounded by a plurality of upper gate structures, respectively; and at least one of a lower diffusion break structure on the lower stack and a upper diffusion break structure on the upper stack, wherein the lower diffusion break structure is formed between two adjacent lower gate structures, and isolates two lower transistor structures respectively including the two adjacent lower gate structures from each other, and the upper diffusion break structure is formed between two adjacent upper gate structures, and isolates two upper transistor structures respectively including the two adjacent upper gate structures from each other.

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