公开(公告)号：US12041760B2

公开(公告)日：2024-07-16

申请号：US17884442

申请日：2022-08-09

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chih-Yu Hsu ,  Jian-Hao Chen ,  Chia-Wei Chen ,  Shan-Mei Liao ,  Hui-Chi Chen ,  Yu-Chia Liang ,  Shih-Hao Lin ,  Kuei-Lun Lin ,  Kuo-Feng Yu ,  Feng-Cheng Yang ,  Yen-Ming Chen

IPC: H01L27/11 ,  H10B10/00

CPC classification number: H10B10/12

Abstract: A transistor includes a gate structure that has a first gate dielectric layer and a second gate dielectric layer. The first gate dielectric layer is disposed over the substrate. The first gate dielectric layer contains a first type of dielectric material that has a first dielectric constant. The second gate dielectric layer is disposed over the first gate dielectric layer. The second gate dielectric layer contains a second type of dielectric material that has a second dielectric constant. The second dielectric constant is greater than the first dielectric constant. The first dielectric constant and the second dielectric constant are each greater than a dielectric constant of silicon oxide.

公开(公告)号：US12035518B2

公开(公告)日：2024-07-09

申请号：US17871603

申请日：2022-07-22

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ka-Hing Fung

IPC: H01L27/11 ,  G06F30/392 ,  G11C11/412 ,  H01L27/092 ,  H01L29/78 ,  H10B10/00

CPC classification number: H10B10/12 ,  G06F30/392 ,  G11C11/412 ,  H01L27/0924 ,  H01L29/785 ,  H01L2029/7858

Abstract: A semiconductor device includes a first region, a second region, a third region, and a fourth region. The first region includes a first portion of an N-well and a plurality of P-type transistors formed over the first portion of the N-well. The first region extends in a first direction. The second region includes a first portion of a P-well and a plurality of N-type transistors formed over the first portion of the P-well. The second region extends in the first direction. The third region includes a second portion of the P-well. The fourth region includes a second portion of the N-well. The first region and the second region are disposed between the third region and the fourth region.

公开(公告)号：US11990464B2

公开(公告)日：2024-05-21

申请号：US17204797

申请日：2021-03-17

Applicant: SOCIONEXT INC.

Inventor： Toru Matsui

IPC: H01L27/02 ,  H01L27/11 ,  H01L27/118

CPC classification number: H01L27/0207 ,  H01L27/11898 ,  H01L2224/0613 ,  H01L2224/06134 ,  H01L2224/0616 ,  H01L2224/06163 ,  H01L2224/06177

Abstract: Provided is a semiconductor integrated circuit device including a plurality of columns of IO cells and having a configuration capable of reducing wiring delays without causing an increase in the area. The semiconductor integrated circuit device includes a first IO cell column group including an IO cell column closest to a periphery of a chip, and a second IO cell column group including an IO cell column adjacent to the first IO cell column group at the side closer to the core region. At least one of the first IO cell column group or the second IO cell column group includes two or more IO cell columns, and the two or more IO cell columns are aligned in the second direction such that the lower power supply voltage regions face each other or the higher power supply voltage regions face each other.

公开(公告)号：US20240121933A1

公开(公告)日：2024-04-11

申请号：US17960222

申请日：2022-10-05

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Gen Tsutsui ,  Shogo Mochizuki ,  Ruilong Xie

IPC: H01L27/11

CPC classification number: H01L27/1108

Abstract: A semiconductor structure is presented including a bottom field effect transistor (FET) including a plurality of bottom source/drain (S/D) epi regions, a top FET including a plurality of top S/D epi regions, a bonding dielectric layer disposed directly between the bottom FET and the top FET, and a node contact advantageously extending from a bottom S/D epi region of the plurality of bottom S/D epi regions of the bottom FET through the bonding dielectric layer and into the top FET. The bottom FET includes an inverter gate. The top FET electrically connects to back-end-of-line (BEOL) components and the bottom FET electrically connects to a backside power delivery network (BSPDN).

公开(公告)号：US20240074135A1

公开(公告)日：2024-02-29

申请号：US17822146

申请日：2022-08-25

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Nicolas Jean Loubet ,  Kirsten Emilie Moselund ,  Bogdan Cezar Zota

IPC: H01L27/11

CPC classification number: H01L27/1108

Abstract: A microelectronic structure including a bottom transistor having a gate region aligned along a first axis. An upper transistor located on top of the bottom transistor, where the upper transistor has a gate region that is aligned along a second axis, and where the second axis is perpendicular to the first axis.

公开(公告)号：US20240072137A1

公开(公告)日：2024-02-29

申请号：US17900639

申请日：2022-08-31

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Li-Hui Chen ,  Chun-Hung Chen ,  Jhon Jhy Liaw

IPC: H01L29/417 ,  H01L27/02 ,  H01L27/11 ,  H01L27/12 ,  H01L29/78

CPC classification number: H01L29/41775 ,  H01L27/0207 ,  H01L27/1108 ,  H01L27/1237 ,  H01L29/41791 ,  H01L29/7831 ,  H01L29/7855

Abstract: A first transistor includes a first gate, a first source/drain, and a first source/drain contact disposed over the first source/drain. The first gate has a first dimension measured in a first lateral direction. The first source/drain contact has a second dimension measured in the first lateral direction. A second transistor includes a second gate, a second source/drain, and a second source/drain contact disposed over the second source/drain. The second gate has a third dimension measured in the first lateral direction. The second source/drain contact has a fourth dimension measured in the first lateral direction. A first ratio of the first dimension and the second dimension is different from a second ratio of the third dimension and the fourth dimension.

公开(公告)号：US11901361B2

公开(公告)日：2024-02-13

申请号：US17814842

申请日：2022-07-26

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.

Inventor： Jia-Ni Yu ,  Kuo-Cheng Chiang ,  Lung-Kun Chu ,  Chung-Wei Hsu ,  Chih-Hao Wang ,  Mao-Lin Huang

IPC: H01L27/092 ,  H01L29/06 ,  H01L29/10 ,  H01L29/04 ,  H01L21/8238 ,  H01L29/423 ,  H01L27/02 ,  H01L27/11 ,  H01L29/786 ,  H10B10/00

CPC classification number: H01L27/0922 ,  H01L21/823807 ,  H01L21/823821 ,  H01L21/823842 ,  H01L27/0207 ,  H01L27/0924 ,  H01L29/045 ,  H01L29/0673 ,  H01L29/1037 ,  H01L29/42392 ,  H01L29/78696 ,  H10B10/12

Abstract: A semiconductor structure includes a first FET device, a second FET device disposed, and an isolation separating the first FET device and the second FET device. The first FET device includes a fin structure, a first work function metal layer disposed over the fin structure, and a high-k gate dielectric layer between the first work function metal layer and the fin structure. The second FET device includes a plurality of nanosheets separated from each other, a second work function metal layer surrounding each of the nanosheets, and the high-k gate dielectric layer between the second work function metal layer and each of the nanosheets. A portion of the high-k gate dielectric layer is directly over the isolation.

公开(公告)号：US11894373B2

公开(公告)日：2024-02-06

申请号：US17083342

申请日：2020-10-29

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Po-Yu Yang

IPC: H01L27/092 ,  H01L27/11 ,  H01L21/8234 ,  H01L21/822 ,  H10B10/00

CPC classification number: H01L27/092 ,  H01L21/8221 ,  H01L21/823412 ,  H01L21/823418 ,  H01L21/823437 ,  H01L21/823475 ,  H10B10/125

Abstract: A semiconductor device includes a substrate, a first transistor and a second transistor disposed on the substrate, and a first contact structure. The first transistor includes first semiconductor channel layers stacked and separated from one another, and a first source/drain structure and a second source/drain structure disposed at two opposite sides of and connected with each first semiconductor channel layer. The second transistor includes second semiconductor channel layers disposed above the first semiconductor channel layers, stacked, and separated from one another, and a third source/drain structure and a fourth source/drain structure disposed at two opposite sides of and connected with each second semiconductor channel layer. The first contact structure penetrates through the third source/drain structure. The first source/drain structure is electrically connected with the third source/drain structure via the first contact structure, and a part of the first source/drain structure is disposed between the substrate and the first contact structure.

公开(公告)号：US20240038297A1

公开(公告)日：2024-02-01

申请号：US17874611

申请日：2022-07-27

Applicant: Arm Limited

Inventor： Rahul Mathur ,  Mudit Bhargava

IPC: G11C11/419 ,  G11C11/412 ,  H01L27/11

CPC classification number: G11C11/419 ,  G11C11/412 ,  H01L27/1104

Abstract: Various implementations described herein are related to a device having bitline drivers coupled to passgates of bitcells via bitlines and buried metal lines formed within a substrate including a buried enable signal line and a buried ground line coupled to ground connections of the bitline drivers. The buried enable signal line transfers a negative bias to a selected bitline of the bitlines via the buried ground line that is coupled to the ground connections of the bitline drivers so as to increase gate-source bias of the passgates of the selected bitcell to thereby enhance write capability of the selected bitcell.

公开(公告)号：US11887838B2

公开(公告)日：2024-01-30

申请号：US17867369

申请日：2022-07-18

Applicant: Intel Corporation

Inventor： Anthony St. Amour ,  Michael L. Hattendorf ,  Christopher P. Auth

IPC: H01L21/8234 ,  H01L49/02 ,  H01L21/762 ,  H01L21/8238 ,  H01L21/311 ,  H01L29/08 ,  H01L27/11 ,  H01L29/78 ,  H01L29/66 ,  H01L21/308 ,  H01L27/092 ,  H01L29/51 ,  H01L21/285 ,  H01L21/28 ,  H01L21/033 ,  H01L21/768 ,  H01L23/532 ,  H01L23/522 ,  H01L23/528 ,  H01L29/417 ,  H01L27/088 ,  H10B10/00

CPC classification number: H01L21/823475 ,  H01L21/0337 ,  H01L21/28247 ,  H01L21/28568 ,  H01L21/3086 ,  H01L21/31105 ,  H01L21/31144 ,  H01L21/76224 ,  H01L21/76816 ,  H01L21/823431 ,  H01L21/823481 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/823842 ,  H01L21/823857 ,  H01L21/823871 ,  H01L21/823878 ,  H01L23/5226 ,  H01L23/5283 ,  H01L23/53238 ,  H01L23/53266 ,  H01L27/0886 ,  H01L27/0924 ,  H01L28/24 ,  H01L29/0847 ,  H01L29/41791 ,  H01L29/516 ,  H01L29/6653 ,  H01L29/66795 ,  H01L29/785 ,  H01L29/7843 ,  H01L29/7846 ,  H01L29/7854 ,  H10B10/12

Abstract: Embodiments of the disclosure are in the field of advanced integrated circuit structure fabrication and, in particular, 10 nanometer node and smaller integrated circuit structure fabrication and the resulting structures. In an example, an integrated circuit structure includes a fin comprising silicon. A plurality of gate structures is over the fin, individual ones of the plurality of gate structures along a direction orthogonal to the fin and having a pair of dielectric sidewall spacers. A trench contact structure is over the fin and directly between the dielectric sidewalls spacers of a first pair of the plurality of gate structures. A contact plug is over the fin and directly between the dielectric sidewalls spacers of a second pair of the plurality of gate structures, the contact plug comprising a lower dielectric material and an upper hardmask material.