公开(公告)号：US20240363697A1

公开(公告)日：2024-10-31

申请号：US18351784

申请日：2023-07-13

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Yi-An Lai ,  Chan-Hong Chern ,  Pen Chieh Yu ,  Cheng-Hsiang Hsieh

IPC: H01L29/40 ,  H01L21/311 ,  H01L21/3213 ,  H01L29/06 ,  H01L29/205 ,  H01L29/417 ,  H01L29/423

CPC classification number: H01L29/405 ,  H01L21/31105 ,  H01L21/3213 ,  H01L29/0649 ,  H01L29/205 ,  H01L29/401 ,  H01L29/41775 ,  H01L29/42316 ,  H01L29/66431 ,  H01L29/7786

Abstract: Various embodiments of the present disclosure are directed towards a semiconductor device comprising a plurality of quasi field plates (QFPs) for enhanced wafer uniformity and performance. A channel layer and a barrier layer are stacked on a substrate, and the channel layer accommodates a two-dimensional carrier gas (2DCG). A source electrode, a drain electrode, and a gate electrode overlie the channel and barrier layers, and the gate electrode is between the source and drain electrodes in a first direction. The plurality of QFPs are between the gate electrode and the drain electrode. Further, the plurality of QFPs are capacitively or directly electrically coupled to the drain electrode, and are spaced from each other laterally in a line in a second direction transverse to the first direction.

公开(公告)号：US12125783B2

公开(公告)日：2024-10-22

申请号：US18133970

申请日：2023-04-12

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chung-Liang Cheng ,  Shih Wei Bih ,  Yen-Yu Chen

IPC: H01L23/522 ,  H01L21/3105 ,  H01L21/311 ,  H01L21/768 ,  H01L21/02

CPC classification number: H01L23/5226 ,  H01L21/3105 ,  H01L21/31105 ,  H01L21/76802 ,  H01L21/76831 ,  H01L21/02164 ,  H01L21/02252 ,  H01L21/31116 ,  H01L21/76843

Abstract: A semiconductor device includes: a first conductive structure having sidewalls and a bottom surface, the first conductive structure extending through one or more isolation layers formed on a substrate; and an insulation layer disposed between at least one of the sidewalls of the first conductive structure and respective sidewalls of the one or more isolation layers, wherein the first conductive structure is electrically coupled to a second conductive structure through at least the bottom surface.

公开(公告)号：US20240312820A1

公开(公告)日：2024-09-19

申请号：US18595341

申请日：2024-03-04

Applicant: Kioxia Corporation

Inventor： Yoshio MIZUTA

IPC: H01L21/68 ,  G03F7/00 ,  H01L21/66 ,  H01L21/67 ,  H01L23/00 ,  H01L21/311 ,  H01L21/683

CPC classification number: H01L21/68 ,  G03F7/70775 ,  H01L21/67092 ,  H01L21/67288 ,  H01L22/20 ,  H01L24/80 ,  H01L21/31105 ,  H01L21/6838 ,  H01L24/05 ,  H01L24/08 ,  H01L2224/05647 ,  H01L2224/08145 ,  H01L2224/80123 ,  H01L2224/80357 ,  H01L2224/80379 ,  H01L2224/80896 ,  H01L2924/05042 ,  H01L2924/05442

Abstract: According to embodiments, a semiconductor manufacturing apparatus includes a control circuit configured to acquire, for a pair of substrates including a first substrate and a second substrate, a warp amount of the first substrate, the warp amount of the first substrate including an amount of protrusion of a portion of the first substrate relative to an edge of the first substrate; determine a desired size for a gap between the first and second substrates based on the acquired warp amount; and control a chuck movement device to move one of the first and second substrates to adjust the gap to the determined size before the first and second substrates are bonded.

公开(公告)号：US12080782B2

公开(公告)日：2024-09-03

申请号：US18201868

申请日：2023-05-25

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jun Noh Lee

IPC: H01L29/66 ,  H01L21/311 ,  H01L21/3213 ,  H10B41/27 ,  H10B43/27

CPC classification number: H01L29/66833 ,  H01L21/31105 ,  H01L21/32139 ,  H01L29/66666 ,  H10B41/27 ,  H10B43/27

Abstract: A method of forming a semiconductor device includes forming, on a lower structure, a mold structure having interlayer insulating layers and gate layers alternately and repeatedly stacked. Each of the gate layers is formed of a first layer, a second layer, and a third layer sequentially stacked. The first and third layers include a first material, and the second layer includes a second material having an etch selectivity different from an etch selectivity of the first material. A hole formed to pass through the mold structure exposes side surfaces of the interlayer insulating layers and side surfaces of the gate layers. Gate layers exposed by the hole are etched, with an etching speed of the second material differing from an etching speed of the first material, to create recessed regions.

公开(公告)号：US11948997B2

公开(公告)日：2024-04-02

申请号：US18135624

申请日：2023-04-17

Applicant: Intel Corporation

Inventor： Subhash M. Joshi ,  Jeffrey S. Leib ,  Michael L. Hattendorf

IPC: H01L29/66 ,  H01L21/02 ,  H01L21/033 ,  H01L21/28 ,  H01L21/285 ,  H01L21/308 ,  H01L21/311 ,  H01L21/762 ,  H01L21/768 ,  H01L21/8234 ,  H01L21/8238 ,  H01L23/522 ,  H01L23/528 ,  H01L23/532 ,  H01L27/02 ,  H01L27/088 ,  H01L27/092 ,  H01L29/06 ,  H01L29/08 ,  H01L29/165 ,  H01L29/167 ,  H01L29/417 ,  H01L29/51 ,  H01L29/78 ,  H01L49/02 ,  H10B10/00 ,  H01L23/00

CPC classification number: H01L29/66545 ,  H01L21/02532 ,  H01L21/02636 ,  H01L21/0337 ,  H01L21/28247 ,  H01L21/28518 ,  H01L21/28568 ,  H01L21/3086 ,  H01L21/31105 ,  H01L21/31144 ,  H01L21/76224 ,  H01L21/76232 ,  H01L21/76801 ,  H01L21/76802 ,  H01L21/76816 ,  H01L21/76834 ,  H01L21/76846 ,  H01L21/76849 ,  H01L21/76877 ,  H01L21/76897 ,  H01L21/823431 ,  H01L21/823481 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/823828 ,  H01L21/823842 ,  H01L21/823857 ,  H01L21/823871 ,  H01L21/823878 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/5283 ,  H01L23/53209 ,  H01L23/53238 ,  H01L23/53266 ,  H01L23/5329 ,  H01L27/0207 ,  H01L27/0886 ,  H01L27/0922 ,  H01L27/0924 ,  H01L28/20 ,  H01L28/24 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/165 ,  H01L29/167 ,  H01L29/41783 ,  H01L29/41791 ,  H01L29/516 ,  H01L29/6653 ,  H01L29/6656 ,  H01L29/66636 ,  H01L29/66795 ,  H01L29/66818 ,  H01L29/7843 ,  H01L29/7845 ,  H01L29/7846 ,  H01L29/7848 ,  H01L29/785 ,  H01L29/7851 ,  H01L29/7854 ,  H10B10/12 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/0332 ,  H01L21/76883 ,  H01L21/76885 ,  H01L21/823437 ,  H01L21/823475 ,  H01L24/16 ,  H01L24/32 ,  H01L24/73 ,  H01L29/665 ,  H01L29/7842 ,  H01L29/7853 ,  H01L2224/16227 ,  H01L2224/32225 ,  H01L2224/73204

Abstract: Embodiments of the disclosure are in the field of advanced integrated circuit structure fabrication and, in particular, 10 nanometer node and smaller integrated circuit structure fabrication and the resulting structures. In an example, an integrated circuit structure includes a fin. A gate dielectric layer is over the top of the fin and laterally adjacent the sidewalls of the fin. A gate electrode is over the gate dielectric layer over the top of the fin and laterally adjacent the sidewalls of the fin. First and second semiconductor source or drain regions are adjacent the first and second sides of the gate electrode, respectively. First and second trench contact structures are over the first and second semiconductor source or drain regions, respectively, the first and second trench contact structures both comprising a U-shaped metal layer and a T-shaped metal layer on and over the entirety of the U-shaped metal layer.

公开(公告)号：US20240096796A1

公开(公告)日：2024-03-21

申请号：US18219244

申请日：2023-07-07

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Yongjin KIM ,  Sanghoon AHN

IPC: H01L23/528 ,  H01L21/768 ,  H01L23/522 ,  H01L23/532

CPC classification number: H01L23/5283 ,  H01L21/76816 ,  H01L21/76831 ,  H01L21/76832 ,  H01L21/76846 ,  H01L23/5226 ,  H01L23/53238 ,  H01L23/53266 ,  H01L23/53295 ,  H01L21/31105

Abstract: An integrated circuit device includes a plurality of wiring structures on a substrate and extending in a first direction parallel to an upper surface of the substrate and each including a wiring layer on the substrate and extending in a direction perpendicular to the upper surface of the substrate; an insulating pattern surrounding a sidewall of the wiring layer and including a first insulating material; and a capping layer on an upper surface of the wiring layer and including a conductive material; a via layer on the wiring structures, the via layer being electrically connected to one wiring structure; and an interlayer insulating layer covering a sidewall of the insulating pattern between each wiring structure of the plurality of wiring structures, the interlayer insulating layer having an upper surface higher than an upper surface of each wiring layer and an upper surface of each insulating pattern.

公开(公告)号：US20240038578A1

公开(公告)日：2024-02-01

申请号：US18376763

申请日：2023-10-04

Applicant: Intel Corporation

Inventor： Heidi M. MEYER ,  Ahmet TURA ,  Byron HO ,  Subhash JOSHI ,  Michael L. HATTENDORF ,  Christopher P. AUTH

IPC: H01L21/762 ,  H01L21/8234 ,  H01L21/8238 ,  H01L21/311 ,  H01L29/08 ,  H01L29/78 ,  H01L29/66 ,  H01L21/308 ,  H01L27/092 ,  H01L29/51 ,  H01L21/285 ,  H01L21/28 ,  H01L21/033 ,  H01L21/768 ,  H01L23/532 ,  H01L23/522 ,  H01L23/528 ,  H01L27/088 ,  H10B10/00

CPC classification number: H01L21/76224 ,  H01L28/24 ,  H01L21/823481 ,  H01L21/823431 ,  H01L21/823878 ,  H01L21/823807 ,  H01L21/823821 ,  H01L21/31144 ,  H01L21/31105 ,  H01L29/0847 ,  H01L29/7843 ,  H01L29/7846 ,  H01L29/6653 ,  H01L21/3086 ,  H01L27/0924 ,  H01L29/516 ,  H01L21/823857 ,  H01L21/823842 ,  H01L21/823814 ,  H01L21/823871 ,  H01L21/28568 ,  H01L21/28247 ,  H01L21/0337 ,  H01L21/76816 ,  H01L23/53238 ,  H01L23/53266 ,  H01L23/5226 ,  H01L23/5283 ,  H01L29/7854 ,  H01L29/66795 ,  H01L29/7848 ,  H01L29/66818 ,  H01L27/0886 ,  H01L29/785 ,  H10B10/12

Abstract: Embodiments of the disclosure are in the field of advanced integrated circuit structure fabrication and, in particular, 10 nanometer node and smaller integrated circuit structure fabrication and the resulting structures. In an example, an integrated circuit structure includes a fin. An insulating structure is directly adjacent sidewalls of the lower fin portion of the fin. A first gate electrode is over the upper fin portion and over a first portion of the insulating structure. A second gate electrode is over the upper fin portion and over a second portion of the insulating structure. A first dielectric spacer is along a sidewall of the first gate electrode. A second dielectric spacer is along a sidewall of the second gate electrode, the second dielectric spacer continuous with the first dielectric spacer over a third portion of the insulating structure between the first gate electrode and the second gate electrode.

公开(公告)号：US11887891B2

公开(公告)日：2024-01-30

申请号：US18098029

申请日：2023-01-17

Applicant: Intel Corporation

Inventor： Mark T. Bohr ,  Tahir Ghani ,  Nadia M. Rahhal-Orabi ,  Subhash M. Joshi ,  Joseph M. Steigerwald ,  Jason W. Klaus ,  Jack Hwang ,  Ryan Mackiewicz

IPC: H01L21/768 ,  H01L29/78 ,  H01L29/49 ,  H01L29/66 ,  H01L29/51 ,  H01L21/28 ,  H01L21/283 ,  H01L21/311 ,  H01L23/522 ,  H01L23/528 ,  H01L29/08 ,  H01L29/423 ,  H01L29/16 ,  H01L29/45 ,  H01L21/285 ,  H01L23/535

CPC classification number: H01L21/76897 ,  H01L21/283 ,  H01L21/28123 ,  H01L21/28229 ,  H01L21/28255 ,  H01L21/28562 ,  H01L21/31105 ,  H01L21/76802 ,  H01L21/76831 ,  H01L21/76849 ,  H01L21/76877 ,  H01L23/528 ,  H01L23/5226 ,  H01L23/535 ,  H01L29/0847 ,  H01L29/16 ,  H01L29/42364 ,  H01L29/456 ,  H01L29/4966 ,  H01L29/512 ,  H01L29/517 ,  H01L29/518 ,  H01L29/665 ,  H01L29/6656 ,  H01L29/66477 ,  H01L29/66545 ,  H01L29/78 ,  H01L29/785 ,  H01L29/495 ,  H01L2029/7858 ,  H01L2924/0002 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A transistor comprises a substrate, a pair of spacers on the substrate, a gate dielectric layer on the substrate and between the pair of spacers, a gate electrode layer on the gate dielectric layer and between the pair of spacers, an insulating cap layer on the gate electrode layer and between the pair of spacers, and a pair of diffusion regions adjacent to the pair of spacers. The insulating cap layer forms an etch stop structure that is self aligned to the gate and prevents the contact etch from exposing the gate electrode, thereby preventing a short between the gate and contact. The insulator-cap layer enables self-aligned contacts, allowing initial patterning of wider contacts that are more robust to patterning limitations.

公开(公告)号：US20240030316A1

公开(公告)日：2024-01-25

申请号：US17869115

申请日：2022-07-20

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Lo-Heng CHANG ,  Li-Zhen YU ,  Lin-Yu HUANG ,  Huan-Chieh SU ,  Chih-Hao WANG

IPC: H01L29/66 ,  H01L29/423 ,  H01L29/06 ,  H01L21/311 ,  H01L29/775

CPC classification number: H01L29/66795 ,  H01L29/42392 ,  H01L29/0673 ,  H01L21/31105 ,  H01L29/66545 ,  H01L29/775

Abstract: A method includes forming a semiconductor strip and semiconductor layers vertically stacked over a front side of the semiconductor strip; forming a gate structure over the semiconductor layers; etching the semiconductor strip to form recesses in the semiconductor strip and on opposite sides of the gate structure; forming epitaxial layers in the recesses, respectively; forming isolation layers over the epitaxial layers, respectively; forming epitaxial source/drain structures over the isolation layers, respectively; performing an etching process from a backside of the semiconductor strip to form a via opening extending through the semiconductor strip, one of the epitaxial layer, and one of the isolation layer, wherein one of the epitaxial source/drain structures is exposed through the via opening; and forming a backside via in the via opening.

公开(公告)号：US20240030067A1

公开(公告)日：2024-01-25

申请号：US18374976

申请日：2023-09-29

Applicant: Intel Corporation

Inventor： Mark T. BOHR ,  Tahir GHANI ,  Nadia M. RAHHAL-ORABI ,  Subhash M. JOSHI ,  Joseph M. STEIGERWALD ,  Jason W. KLAUS ,  Jack HWANG ,  Ryan MACKIEWICZ

IPC: H01L21/768 ,  H01L29/78 ,  H01L29/49 ,  H01L29/66 ,  H01L29/51 ,  H01L21/28 ,  H01L21/283 ,  H01L21/311 ,  H01L23/522 ,  H01L23/528 ,  H01L29/08 ,  H01L29/423 ,  H01L29/16 ,  H01L29/45 ,  H01L21/285 ,  H01L23/535

CPC classification number: H01L21/76897 ,  H01L29/785 ,  H01L21/76831 ,  H01L21/76849 ,  H01L29/4966 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66477 ,  H01L29/517 ,  H01L29/78 ,  H01L21/28229 ,  H01L21/28255 ,  H01L21/283 ,  H01L21/31105 ,  H01L21/76802 ,  H01L21/76877 ,  H01L23/5226 ,  H01L23/528 ,  H01L29/0847 ,  H01L29/42364 ,  H01L29/512 ,  H01L29/518 ,  H01L29/665 ,  H01L29/16 ,  H01L29/456 ,  H01L21/28123 ,  H01L21/28562 ,  H01L23/535 ,  H01L2029/7858 ,  H01L29/495 ,  H01L2924/0002

Abstract: A transistor comprises a substrate, a pair of spacers on the substrate, a gate dielectric layer on the substrate and between the pair of spacers, a gate electrode layer on the gate dielectric layer and between the pair of spacers, an insulating cap layer on the gate electrode layer and between the pair of spacers, and a pair of diffusion regions adjacent to the pair of spacers. The insulating cap layer forms an etch stop structure that is self aligned to the gate and prevents the contact etch from exposing the gate electrode, thereby preventing a short between the gate and contact. The insulator-cap layer enables self-aligned contacts, allowing initial patterning of wider contacts that are more robust to patterning limitations.