公开(公告)号：US20240363759A1

公开(公告)日：2024-10-31

申请号：US18768357

申请日：2024-07-10

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shih-Cheng Chen ,  Kuo-Cheng Chiang ,  Zhi-Chang Lin

IPC: H01L29/786 ,  H01L21/02 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/06 ,  H01L29/423 ,  H01L29/66

CPC classification number: H01L29/78612 ,  H01L21/02236 ,  H01L21/02532 ,  H01L21/02603 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823864 ,  H01L27/0921 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/66742 ,  H01L29/78618 ,  H01L29/78696

Abstract: A semiconductor device according to the present disclosure includes an active region including a channel region and a source/drain region adjacent the channel region, a vertical stack of channel members over the channel region, a gate structure over and around the vertical stack of channel members, a bottom dielectric feature over the source/drain region, a source/drain feature over the bottom dielectric feature, and a germanium layer disposed between the bottom dielectric feature and the source/drain region.

公开(公告)号：US20240363701A1

公开(公告)日：2024-10-31

申请号：US18492327

申请日：2023-10-23

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jongryeol Yoo

IPC: H01L29/417 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/06 ,  H01L29/423 ,  H01L29/66 ,  H01L29/775 ,  H01L29/786

CPC classification number: H01L29/41733 ,  H01L21/823807 ,  H01L21/823814 ,  H01L27/092 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/775 ,  H01L29/78696

Abstract: The present disclosure relates to semiconductor devices and their fabrication methods. One example semiconductor device comprises a substrate that includes an active region, an active pattern on the active region, a source/drain pattern on the active pattern, an active contact that extends from a top surface to a sidewall of the source/drain pattern and includes a first part that covers the sidewall of the source/drain pattern and a second part that covers the top surface of the source/drain pattern, a first layer between the source/drain pattern and the first part, and a second layer separated from the first layer and across the first part. Each of the first layer and the second layer includes a silicide layer.

公开(公告)号：US20240363635A1

公开(公告)日：2024-10-31

申请号：US18769548

申请日：2024-07-11

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Guan-Wei Huang ,  Yu-Shan Lu ,  Yu-Bey Wu ,  Jiun-Ming Kuo ,  Yuan-Ching Peng

IPC: H01L27/092 ,  H01L21/02 ,  H01L21/8238 ,  H01L29/06 ,  H01L29/423 ,  H01L29/49 ,  H01L29/66 ,  H01L29/786

CPC classification number: H01L27/0922 ,  H01L21/0259 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/82385 ,  H01L29/0665 ,  H01L29/42392 ,  H01L29/4908 ,  H01L29/66545 ,  H01L29/66742 ,  H01L29/78618 ,  H01L29/78696

Abstract: A semiconductor structure that includes a first semiconductor fin and a second semiconductor fin disposed over a substrate and adjacent to each other, a metal gate stack disposed over the substrate, and source/drain features disposed in each of the first semiconductor fin and the second semiconductor fin to engage with the metal gate stack. The metal gate stack includes a first region disposed over the first semiconductor fin, a second region disposed over the second semiconductor fin, and a third region connecting the first region to the second region in a continuous profile, where the first region is defined by a first gate length and the second region is defined by a second gate length less than the first gate length.

公开(公告)号：US20240363439A1

公开(公告)日：2024-10-31

申请号：US18770861

申请日：2024-07-12

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shiu-Ko JANGJIAN ,  Tzu-Kai LIN ,  Chi-Cherng JENG

IPC: H01L21/8238 ,  H01L21/02 ,  H01L21/324 ,  H01L27/092 ,  H01L29/165 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L21/823821 ,  H01L21/02532 ,  H01L21/324 ,  H01L21/823814 ,  H01L27/0924 ,  H01L29/165 ,  H01L29/66636 ,  H01L29/66795 ,  H01L29/7848 ,  H01L29/785

Abstract: A structure and a formation method of a semiconductor device are provided. The semiconductor device includes a semiconductor substrate and a fin structure over the semiconductor substrate. The semiconductor device also includes a gate stack covering a portion of the fin structure and an epitaxially grown source/drain structure over the fin structure and adjacent to the gate stack. The semiconductor device further includes a semiconductor protection layer over the epitaxially grown source/drain structure. The semiconductor protection layer has an atomic concentration of silicon greater than that of the epitaxially grown source/drain structure.

公开(公告)号：US20240363437A1

公开(公告)日：2024-10-31

申请号：US18770367

申请日：2024-07-11

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Shahaji B. MORE

IPC: H01L21/8238 ,  H01L21/02 ,  H01L27/092 ,  H01L29/04 ,  H01L29/08 ,  H01L29/49 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L21/823814 ,  H01L21/02609 ,  H01L21/823821 ,  H01L21/823864 ,  H01L27/0924 ,  H01L29/045 ,  H01L29/0847 ,  H01L29/4983 ,  H01L29/6656 ,  H01L29/66795 ,  H01L29/7851

Abstract: The present disclosure describes a method of forming a semiconductor device having epitaxial structures with optimized dimensions. The method includes forming first and second fin structures on a substrate, forming a spacer layer on the first and second fin structures, forming a first spacer structure adjacent to the first fin structure, and forming a first epitaxial structure adjacent to the first spacer structure. The first and second fin structures are separated by an isolation layer. The first spacer structure has a first height above the isolation layer. The method further includes forming a second spacer structure adjacent to the second fin structure and forming a second epitaxial structure adjacent to the second spacer structure. The second spacer structure has a second height above the isolation layer greater than the first height. The second epitaxial structure includes a type of dopant different from the first epitaxial structure.

公开(公告)号：US20240347536A1

公开(公告)日：2024-10-17

申请号：US18299663

申请日：2023-04-12

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD. ,  NATIONAL TAIWAN UNIVERSITY

Inventor： Hsin-Cheng LIN ,  Chun-Yi CHENG ,  Ching-Wang YAO ,  Chee-Wee LIU

IPC: H01L27/092 ,  H01L21/02 ,  H01L21/8238 ,  H01L23/528 ,  H01L29/06 ,  H01L29/10 ,  H01L29/417 ,  H01L29/423 ,  H01L29/66 ,  H01L29/775

CPC classification number: H01L27/092 ,  H01L21/02532 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823871 ,  H01L23/5286 ,  H01L29/0673 ,  H01L29/1033 ,  H01L29/41733 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/66545 ,  H01L29/775 ,  H03F3/213

Abstract: An integrated circuit includes a first transistor and a second transistor. The first transistor includes first semiconductor channel layers, first gate structure, and a first source structure and a first drain structure on opposites sides of the first gate structure. The second transistor includes second semiconductor channel layers, second gate structure, and a second source structure and a second drain structure on opposites sides of the second gate structure. The first source structure of the first transistor is electrically coupled to the second drain structure of the second transistor. A thickness of each of the first semiconductor channel layers is less than a thickness of each of the second semiconductor channel layers, and a bandgap of a material of the first semiconductor channel layers is larger than a bandgap of a material of the second semiconductor channel layers.

公开(公告)号：US20240339362A1

公开(公告)日：2024-10-10

申请号：US18295346

申请日：2023-04-04

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Ko-Cheng Liu ,  Chang-Miao Liu ,  Huiling Shang

IPC: H01L21/8238 ,  H01L21/762 ,  H01L27/092

CPC classification number: H01L21/823878 ,  H01L21/76224 ,  H01L21/823814 ,  H01L27/092

Abstract: Semiconductor structures and methods are provided. In an embodiment, a semiconductor structure includes a substrate including a first mesa structure and a second mesa structure, an isolation feature extending between the first mesa structure and the second mesa structure, a first vertical stack of nanostructures directly over the first mesa structure, first source/drain features coupled to the first vertical stack of nanostructures, a dielectric layer comprising a first portion disposed on the isolation feature and a second portion disposed between the first-type source/drain features and the substrate, and a first gate structure wrapping around each nanostructure of the first vertical stack of nanostructures.

公开(公告)号：US12112989B2

公开(公告)日：2024-10-08

申请号：US17815085

申请日：2022-07-26

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shih-Hao Lin ,  Tzu-Hsiang Hsu ,  Chong-De Lien ,  Szu-Chi Yang ,  Hsin-Wen Su ,  Chih-Hsiang Huang

IPC: H01L21/8238 ,  H01L21/306 ,  H01L27/092 ,  H01L29/423 ,  H01L29/66 ,  H01L29/78 ,  H10B10/00

CPC classification number: H01L21/823814 ,  H01L21/30604 ,  H01L21/823821 ,  H01L27/0924 ,  H01L29/42392 ,  H01L29/6656 ,  H01L29/7848 ,  H10B10/12

Abstract: Semiconductor device and the manufacturing method thereof are disclosed herein. An exemplary method comprises forming first and second semiconductor fins in first and second regions of a substrate, respectively; forming first and second dummy gate stacks over the first and second semiconductor fins, respectively, and forming a spacer layer over the first and the second dummy gate stacks; forming a first pattern layer with a thickness along the spacer layer in the first region; form a first source/drain (S/D) trench along the first pattern layer and epitaxially growing a first epitaxial feature therein; removing the first pattern layer to expose the spacer layer; forming a second pattern layer with a different thickness along the spacer layer in the second region; form a second S/D trench along the second pattern layer and epitaxially growing a second epitaxial feature therein; and removing the second pattern layer to expose the spacer layer.

公开(公告)号：US20240332393A1

公开(公告)日：2024-10-03

申请号：US18741963

申请日：2024-06-13

Applicant: Taiwan Semiconductor Manufacturing Company, LTD.

Inventor： Hsu-Kai CHANG ,  Jhih-Rong HUANG ,  Yen-Tien TUNG ,  Chia-Hung CHU ,  Shuen-Shin LIANG ,  Tzer-Min SHEN ,  Pinyen LIN ,  Sung-Li WANG

IPC: H01L29/45 ,  H01L21/285 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/08 ,  H01L29/417 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L29/45 ,  H01L21/28518 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/823871 ,  H01L27/0924 ,  H01L29/0847 ,  H01L29/41791 ,  H01L29/66795 ,  H01L29/7851

Abstract: A semiconductor device with different configurations of contact structures and a method of fabricating the same are disclosed. The semiconductor device includes first and second gate structures disposed on first and second fin structures, first and second source/drain (S/D) regions disposed on the first and second fin structures, first and second contact structures disposed on the first and second S/D regions, and a dipole layer disposed at an interface between the first nWFM silicide layer and the first S/D region. The first contact structure includes a first nWFM silicide layer disposed on the first S/D region and a first contact plug disposed on the first nWFM silicide layer. The second contact structure includes a pWFM silicide layer disposed on the second S/D region, a second nWFM silicide layer disposed on the pWFM silicide layer, and a second contact plug disposed on the pWFM silicide layer.

公开(公告)号：US20240332357A1

公开(公告)日：2024-10-03

申请号：US18193878

申请日：2023-03-31

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hung-Yu Yen ,  Keng-Chu Lin

IPC: H01L29/06 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/417 ,  H01L29/423 ,  H01L29/66 ,  H01L29/775 ,  H01L29/786

CPC classification number: H01L29/0673 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823864 ,  H01L27/092 ,  H01L29/41733 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/66545 ,  H01L29/775 ,  H01L29/78696

Abstract: In an embodiment, a method includes: forming a sacrificial spacer in a contact opening, the contact opening exposing a source/drain region; depositing a spacer layer on a sidewall of the sacrificial spacer and on a top surface of the source/drain region; forming a protective dielectric on the spacer layer and in the contact opening; removing the sacrificial spacer to form a recess adjacent the spacer layer; and forming a dielectric cap in an upper portion of the recess by redepositing a material of the protective dielectric and a material of the spacer layer in the upper portion of the recess, the dielectric cap sealing a lower portion of the recess to form a void.