公开(公告)号：US12062721B2

公开(公告)日：2024-08-13

申请号：US17666240

申请日：2022-02-07

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Shih-Cheng Chen ,  Kuo-Cheng Chiang ,  Zhi-Chang Lin

IPC分类号： H01L29/786 ,  H01L21/02 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/06 ,  H01L29/423 ,  H01L29/66

CPC分类号： H01L29/78612 ,  H01L21/02236 ,  H01L21/02532 ,  H01L21/02603 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823864 ,  H01L27/0921 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/66742 ,  H01L29/78618 ,  H01L29/78696

摘要： A semiconductor device according to the present disclosure includes an active region including a channel region and a source/drain region adjacent the channel region, a vertical stack of channel members over the channel region, a gate structure over and around the vertical stack of channel members, a bottom dielectric feature over the source/drain region, a source/drain feature over the bottom dielectric feature, and a germanium layer disposed between the bottom dielectric feature and the source/drain region.

公开(公告)号：US11756959B2

公开(公告)日：2023-09-12

申请号：US17347218

申请日：2021-06-14

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Ching-Wei Tsai ,  Yu-Xuan Huang ,  Kuan-Lun Cheng ,  Wei Ju Lee ,  Chun-Fu Cheng ,  Chung-Wei Wu

IPC分类号： H01L27/092 ,  H01L21/8238 ,  H01L29/08 ,  H01L29/06 ,  H01L29/78 ,  H01L29/423 ,  H01L29/786 ,  H01L21/265 ,  H01L21/266 ,  H01L21/74 ,  H01L29/66 ,  H01L29/10

CPC分类号： H01L27/0921 ,  H01L21/266 ,  H01L21/26513 ,  H01L21/74 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/823878 ,  H01L21/823892 ,  H01L29/0653 ,  H01L29/0673 ,  H01L29/0847 ,  H01L29/1083 ,  H01L29/42392 ,  H01L29/66537 ,  H01L29/66742 ,  H01L29/66795 ,  H01L29/7851 ,  H01L29/78612 ,  H01L29/78618 ,  H01L29/78696

摘要： The present disclosure provides an integrated circuit that includes a circuit formed on a semiconductor substrate; and a de-cap device formed on the semiconductor substrate and integrated with the circuit. The de-cap device includes a filed-effect transistor (FET) that further includes a source and a drain connected through contact features landing on the source and drain, respectively; a gate stack overlying a channel and interposed between the source and the drain; and a doped feature disposed underlying the channel and connecting to the source and the drain, wherein the doped feature is doped with a dopant of a same type of the source and the drain.

公开(公告)号：US10020394B2

公开(公告)日：2018-07-10

申请号：US15883056

申请日：2018-01-29

申请人： GLOBALFOUNDRIES Singapore Pte. Ltd.

发明人： Rui Tze Toh ,  Guan Huei See ,  Shaoqiang Zhang ,  Purakh Raj Verma

IPC分类号： H01L29/78 ,  H01L29/66 ,  H01L29/10

CPC分类号： H01L29/7824 ,  H01L29/1095 ,  H01L29/665 ,  H01L29/66681 ,  H01L29/66689 ,  H01L29/66742 ,  H01L29/66772 ,  H01L29/78612 ,  H01L29/78615 ,  H01L29/78621 ,  H01L29/78645

摘要： Devices and methods for forming a device are disclosed. A substrate is provided. A first body well of a second polarity type is formed in the substrate. A second body well of the second polarity type is formed in the first body well. A bottom of the second body well and a bottom of the first body well are contiguous. Dopant concentrations of the first and second body wells include a graded profile. A transistor of a first polarity type is formed over the substrate. The transistor includes a source and a drain. The source is formed in the second body well.

公开(公告)号：US10014324B2

公开(公告)日：2018-07-03

申请号：US14528620

申请日：2014-10-30

申请人： Sony Corporation

发明人： Akiko Honjo

IPC分类号： H01L27/12 ,  H01L29/786 ,  H01L27/32

CPC分类号： H01L27/1222 ,  H01L27/1218 ,  H01L27/3262 ,  H01L29/78603 ,  H01L29/78612 ,  H01L29/78621 ,  H01L29/78678 ,  H01L29/7869 ,  H01L29/78693 ,  H01L29/78696

摘要： Provided is a thin film transistor, including: a base that includes, on an upper surface, a first region and a second region; a gate electrode that is provided on the first region of the base; a gate insulating film that is provided on a surface of the gate electrode and the second region of the base; and a semiconductor layer that is provided on a surface of the gate insulating film, wherein the semiconductor layer includes a third region and a fourth region, in the third region, the semiconductor layer and the gate electrode face with a minimum interval, in the fourth region, a distance from the semiconductor layer to the gate electrode is larger than the minimum interval, and at a boundary position between the third region and the fourth region, the semiconductor layer forms a linear shape or a substantially linear shape.

公开(公告)号：US09741857B2

公开(公告)日：2017-08-22

申请号：US14821685

申请日：2015-08-07

申请人： Ahmad Tarakji

发明人： Ahmad Tarakji

IPC分类号： H01L29/786 ,  H01L29/78 ,  H01L27/12

CPC分类号： H01L29/78615 ,  H01L27/1203 ,  H01L29/7838 ,  H01L29/78603 ,  H01L29/78612 ,  H01L29/78618 ,  H01L29/78648 ,  H01L29/78696

摘要： New, distinct, and useful architectures for single-legged SOI-MOS were established and fabricated for the very first time. They incorporated into their architectures an innovative new configuration to wire the device Body to the Body-Tied-Source. This new configuration drastically increased the conductance between the Body and the Body-Tied-Source. This consequently allowed these devices to effectively support much higher operating biases. Same configuration also functioned on structures with very large peripheries. These gave proportional increase in this same conductivity, and for same area-efficiency, with the increase of their peripheries to accommodate higher currents. The functional model that governs this proportional scaling in these new architectures for single-legged SOI-MOS devices was established and is being claimed through this patent for the very first time. Through it, single-legged SOI-MOS devices will efficiently scale to area-efficient ultra large peripheries with minimal hits to their bandwidth.

公开(公告)号：US20170040461A1

公开(公告)日：2017-02-09

申请号：US14821685

申请日：2015-08-07

申请人： Ahmad Tarakji

发明人： Ahmad Tarakji

IPC分类号： H01L29/786 ,  H01L29/78

CPC分类号： H01L29/78615 ,  H01L27/1203 ,  H01L29/7838 ,  H01L29/78603 ,  H01L29/78612 ,  H01L29/78618 ,  H01L29/78648 ,  H01L29/78696

摘要： The invention provides the guided design approach to optimize the device performance for a best area-efficient layout footprint in a single-leg MOS device that is based on any of the SOI, SOS or SON technologies. The design methodology depends on a new proprietary device architecture that is also being claimed in this patent and that allows the implementations of the design equations of our methodology.

摘要翻译： 本发明提供了一种引导设计方法，以便在基于任何SOI，SOS或SON技术的单脚MOS器件中优化器件性能，实现最佳区域高效布局。 该设计方法取决于在该专利中也被要求保护的新的专用设备架构，并且允许实现我们的方法的设计方程式。

公开(公告)号：US09406569B2

公开(公告)日：2016-08-02

申请号：US14519493

申请日：2014-10-21

申请人： GLOBALFOUNDRIES INC.

发明人： Gregory G. Freeman ,  Kam Leung Lee ,  Chengwen Pei ,  Geng Wang ,  Yanli Zhang

IPC分类号： H01L27/108 ,  H01L29/78 ,  H01L21/84 ,  H01L21/265 ,  H01L29/66 ,  H01L27/12 ,  H01L29/786 ,  H01L29/06 ,  H01L21/324 ,  H01L21/762

CPC分类号： H01L21/84 ,  H01L21/26506 ,  H01L21/26586 ,  H01L21/3247 ,  H01L21/76243 ,  H01L27/1087 ,  H01L27/10873 ,  H01L27/1203 ,  H01L29/0623 ,  H01L29/66181 ,  H01L29/78 ,  H01L29/78603 ,  H01L29/78612 ,  H01L29/78687 ,  H01L29/78696

摘要： A semiconductor-on-insulator (SOI) substrate comprises a bulk semiconductor substrate, a buried insulator layer formed on the bulk substrate and an active semiconductor layer formed on the buried insulator layer. Impurities are implanted near the interface of the buried insulator layer and the active semiconductor layer. A diffusion barrier layer is formed between the impurities and an upper surface of the active semiconductor layer. The diffusion barrier layer prevents the impurities from diffusing therethrough.

摘要翻译： 绝缘体上半导体（SOI）衬底包括体半导体衬底，形成在本体衬底上的掩埋绝缘体层和形成在掩埋绝缘体层上的有源半导体层。 杂质植入到埋入绝缘体层和有源半导体层的界面附近。 在杂质和有源半导体层的上表面之间形成扩散阻挡层。 扩散阻挡层防止杂质从其中扩散。

公开(公告)号：US09379249B2

公开(公告)日：2016-06-28

申请号：US14219385

申请日：2014-03-19

申请人： LG Display Co., Ltd.

发明人： KwangHwan Ji ,  DaeHwan Kim ,  JunHyeon Bae

IPC分类号： H01L29/786 ,  H01L27/12 ,  H01L29/66

CPC分类号： H01L29/7869 ,  H01L27/1225 ,  H01L29/4908 ,  H01L29/66969 ,  H01L29/78612 ,  H01L29/78696

摘要： A thin-film transistor includes a substrate, a first gate electrode formed on the substrate, a first active layer that is formed on the substrate and includes a first oxide semiconductor layer and a first barrier layer, a second active layer that is formed on the first active layer and includes a second oxide semiconductor layer and an intermediate barrier layer, a gate insulating layer that is formed on the second active layer, a second gate electrode that is formed on the gate insulating layer and is electrically connected to the first gate electrode, an interlayer insulating film formed on the second gate electrode, the first active layer and the second active layer, and a source electrode and a drain electrode electrically connected to the first active layer and the second active layer.

摘要翻译： 薄膜晶体管包括基板，形成在基板上的第一栅电极，形成在基板上并包括第一氧化物半导体层和第一势垒层的第一有源层，形成在第一有源层上的第二有源层， 第一有源层，并且包括第二氧化物半导体层和中间阻挡层，形成在第二有源层上的栅极绝缘层，形成在栅极绝缘层上并与第一栅电极电连接的第二栅电极 形成在第二栅电极，第一有源层和第二有源层上的层间绝缘膜，以及与第一有源层和第二有源层电连接的源电极和漏电极。

公开(公告)号：US20160118406A1

公开(公告)日：2016-04-28

申请号：US14521327

申请日：2014-10-22

申请人： QUALCOMM SWITCH CORP.

发明人： Paul A. Nygaard ,  Michael A. Stuber

IPC分类号： H01L27/12 ,  H01L29/872 ,  H01L29/78 ,  H01L29/47 ,  H01L21/3205 ,  H01L21/84 ,  H01L29/32 ,  H01L29/10 ,  H01L21/265 ,  H01L27/06 ,  H01L29/66

CPC分类号： H01L27/1203 ,  H01L21/265 ,  H01L21/32053 ,  H01L21/84 ,  H01L27/0629 ,  H01L29/1095 ,  H01L29/32 ,  H01L29/47 ,  H01L29/66143 ,  H01L29/66477 ,  H01L29/7839 ,  H01L29/78612 ,  H01L29/872

摘要： A semiconductor structure is formed with an active layer having an active device including a body region. The active device is formed by top side processing in and on a top side of a semiconductor on insulator wafer. A damaged region is formed within a portion of the body region by bottom side processing at a bottom side of the semiconductor on insulator wafer, the damaged region having a structure sufficient to prevent a kink effect and self-latching in operation of the active device.

摘要翻译： 半导体结构形成有具有活性器件的有源层，其包括体区。 有源器件通过在半导体绝缘体晶片的顶侧中和顶侧处理形成。 通过在半导体绝缘体晶片的底侧处的底侧处理，在体区域的一部分内形成受损区域，该受损区域具有足以防止在有源器件的操作中的扭结效应和自锁存的结构。

公开(公告)号：US20160020274A1

公开(公告)日：2016-01-21

申请号：US14396709

申请日：2014-08-15

申请人： INSTITUTE OF MICROELECTRONICS, CHINESE ACADEMY OF SCIENCES

发明人： Jing Xu ,  Jiang Yan ,  Bangming Chen ,  Hongli Wang ,  Bo Tang ,  Zhaoyun Tang ,  Yefeng Xu ,  Chunlong Li ,  Mengmeng Yang

IPC分类号： H01L29/06 ,  H01L21/306 ,  H01L29/66 ,  H01L21/02 ,  H01L29/165 ,  H01L29/78

CPC分类号： H01L29/0653 ,  H01L21/02236 ,  H01L21/02381 ,  H01L21/02532 ,  H01L21/30604 ,  H01L21/76264 ,  H01L29/0649 ,  H01L29/1054 ,  H01L29/165 ,  H01L29/665 ,  H01L29/66651 ,  H01L29/66772 ,  H01L29/78 ,  H01L29/7833 ,  H01L29/78609 ,  H01L29/78612 ,  H01L29/78615 ,  H01L29/78654 ,  H01L29/78687 ,  H01L29/78696

摘要： A semiconductor device, including: a substrate having a first semiconductor material; a second semiconductor layer on the substrate; a third semiconductor layer on the second semiconductor layer and being a device formation region; an isolation structure on both sides of the third semiconductor layer and on the substrate; and an insulating layer below the source and drain regions of the third semiconductor layer and between the isolation structure and the ends of the second semiconductor layer.

摘要翻译： 一种半导体器件，包括：具有第一半导体材料的衬底; 在所述基板上的第二半导体层; 第二半导体层上的第三半导体层，并且是器件形成区域; 在第三半导体层的两侧和基板上的隔离结构; 以及在第三半导体层的源极和漏极区域之下以及隔离结构和第二半导体层的端部之间的绝缘层。