-
公开(公告)号：US12067934B2
公开(公告)日：2024-08-20
申请号：US17411401
申请日：2021-08-25
发明人： Shunpei Yamazaki , Jun Koyama , Hiroyuki Miyake
IPC分类号： G09G3/3208 , G09G3/20 , G09G3/3233 , H01L27/12 , H01L29/786 , H10K59/121 , H10K59/131
CPC分类号： G09G3/3208 , G09G3/2003 , G09G3/3233 , H01L27/1225 , H01L29/78609 , H01L29/7869 , H01L29/78693 , H01L29/78696 , H10K59/1213 , H10K59/131 , G09G2330/021
摘要： Objects are to provide a display device the power consumption of which is reduced, to provide a self-luminous display device the power consumption of which is reduced and which is capable of long-term use in a dark place. A circuit is formed using a thin film transistor in which a highly-purified oxide semiconductor is used and a pixel can keep a certain state (a state in which a video signal has been written). As a result, even in the case of displaying a still image, stable operation is easily performed. In addition, an operation interval of a driver circuit can be extended, which results in a reduction in power consumption of a display device. Moreover, a light-storing material is used in a pixel portion of a self-luminous display device to store light, whereby the display device can be used in a dark place for a long time.
-
公开(公告)号：US20240266356A1
公开(公告)日：2024-08-08
申请号：US18606724
申请日：2024-03-15
发明人： Shunpei YAMAZAKI
IPC分类号： H01L27/12 , G02F1/1333 , G02F1/13357 , G02F1/1343 , G02F1/1362 , G02F1/1368 , G09G3/34 , G09G3/36 , H01L27/15 , H01L29/04 , H01L29/12 , H01L29/24 , H01L29/66 , H01L29/786 , H10K59/121
CPC分类号： H01L27/1225 , G02F1/133345 , G02F1/134309 , G02F1/136277 , G02F1/1368 , G09G3/3406 , G09G3/3648 , G09G3/3659 , H01L27/153 , H01L29/045 , H01L29/12 , H01L29/24 , H01L29/66742 , H01L29/66969 , H01L29/78609 , H01L29/7869 , G02F1/1336 , G09G2300/08 , G09G2320/0214 , G09G2320/0626 , G09G2360/144 , H10K59/1213
摘要： Disclosed is a display device including a transistor showing extremely low off current. In order to reduce the off current, a semiconductor material whose band gap is greater than that of a silicon semiconductor is used for forming a transistor, and the concentration of an impurity which serves as a carrier donor of the semiconductor material is reduced. Specifically, an oxide semiconductor whose band gap is greater than or equal to 2 eV, preferably greater than or equal to 2.5 eV, more preferably greater than or equal to 3 eV is used for a semiconductor layer of a transistor, and the concentration of an impurity which serves as a carrier donor included is reduced. Consequently, the off current of the transistor per micrometer in channel width can be reduced to lower than 10 zA/μm at room temperature and lower than 100 zA/μm at 85° C.
-
公开(公告)号：US20240128380A1
公开(公告)日：2024-04-18
申请号：US18526315
申请日：2023-12-01
IPC分类号： H01L29/786 , H01L27/12 , H01L29/45 , H01L29/49 , H01L29/66
CPC分类号： H01L29/78696 , H01L27/1225 , H01L27/1255 , H01L29/45 , H01L29/4908 , H01L29/66969 , H01L29/78609 , H01L29/78648 , H01L29/7869
摘要： A transistor with favorable electrical characteristics is provided. One embodiment of the present invention is a semiconductor device including a semiconductor, a first insulator in contact with the semiconductor, a first conductor in contact with the first insulator and overlapping with the semiconductor with the first insulator positioned between the semiconductor and the first conductor, and a second conductor and a third conductor, which are in contact with the semiconductor. One or more of the first to third conductors include a region containing tungsten and one or more elements selected from silicon, carbon, germanium, tin, aluminum, and nickel.
-
公开(公告)号：US11955555B2
公开(公告)日：2024-04-09
申请号：US17833583
申请日：2022-06-06
申请人： Newport Fab, LLC
发明人： Rula Badarneh , Roda Kanawati , Kurt Moen , Paul D. Hurwitz
IPC分类号： H01L29/786 , H01L21/762 , H01L27/12 , H01L29/40
CPC分类号： H01L29/78609 , H01L21/76202 , H01L21/76224 , H01L27/1203 , H01L29/402
摘要： A field effect transistor (FET) includes an active region including a source region, a drain region, and a channel region. The channel region is under a gate and situated between the source region and the drain region. A field region is next to the active region. The channel region has an interface with the field region. The gate has a wide outer gate segment proximate to the interface and a narrow inner gate segment distant from the interface. The wide outer gate segment produces an outer channel length greater than an inner channel length that is produced from the narrow inner gate segment, thereby reducing a leakage current of the FET during an OFF state.
-
公开(公告)号：US20240088298A1
公开(公告)日：2024-03-14
申请号：US18327217
申请日：2023-06-01
发明人： Keming YANG , Yizhen XU , Chunhui REN , Feng JIANG , Liu HE , Qiang LENG , Rongrong LI
IPC分类号： H01L29/786 , G02F1/1362 , G02F1/1368 , H01L29/417
CPC分类号： H01L29/78609 , G02F1/136222 , G02F1/1368 , H01L29/41733 , H01L29/78696
摘要： Disclosed are a thin film transistor structure, a display panel and a display device. The thin film transistor structure includes a base, a source electrode, a drain electrode configured to connect to a pixel electrode and a grid electrode. The source electrode, the drain electrode and the grid electrode are provided on the base. and a channel is formed between the source electrode and the drain electrode. The thin film transistor structure further includes an insulating layer and a slow-release electrode. The insulating layer is provided on a side of the source electrode and the drain electrode, and filled in the channel. The slow-release electrode is provided in the insulating layer. At least a part of the slow-release electrode is provided inside the channel.
-
公开(公告)号：US11894465B2
公开(公告)日：2024-02-06
申请号：US17174935
申请日：2021-02-12
申请人： Google LLC
发明人： Ravi Pillarisetty , Willy Rachmady , Van H. Le , Seung Hoon Sung , Jessica S. Kachian , Jack T. Kavalieros , Han Wui Then , Gilbert Dewey , Marko Radosavljevic , Benjamin Chu-Kung , Niloy Mukherjee
IPC分类号： H01L29/165 , H01L29/205 , H01L29/786 , H01L29/06 , H01L29/78 , H01L29/423 , H01L29/66
CPC分类号： H01L29/78609 , H01L29/0653 , H01L29/0673 , H01L29/0676 , H01L29/165 , H01L29/205 , H01L29/42392 , H01L29/66742 , H01L29/785 , H01L29/78606 , H01L29/78618 , H01L29/78681 , H01L29/78684 , H01L29/78696
摘要： Deep gate-all-around semiconductor devices having germanium or group 111-V active layers are described. For example, a non-planar semiconductor device includes a hetero-structure disposed above a substrate. The hetero-structure includes a hetero-junction between an upper layer and a lower layer of differing composition. An active layer is disposed above the hetero-structure and has a composition different from the upper and lower layers of the hetero-structure. A gate electrode stack is disposed on and completely surrounds a channel region of the active layer, and is disposed in a trench in the upper layer and at least partially in the lower layer of the hetero-structure. Source and drain regions are disposed in the active layer and in the upper layer, but not in the lower layer, on either side of the gate electrode stack.
-
公开(公告)号：US20230411532A1
公开(公告)日：2023-12-21
申请号：US17814519
申请日：2022-07-24
发明人： Qunfang Liang
IPC分类号： H01L29/786
CPC分类号： H01L29/78696 , H01L29/78609
摘要： A thin film transistor (TFT) device is provided. The TFT device includes a substrate, a semiconductor channel layer, an ohmic contact layer, and a source-drain layer that are sequentially arranged on one side of the substrate. In the channel region, a compensation pattern is disposed on a surface of the semiconductor channel layer away from the substrate. The compensation pattern and the semiconductor channel layer are different types of semiconductors. By disposing the compensation pattern on the surface of the semiconductor channel layer away from the substrate, the compensation pattern and the semiconductor channel layer are different types of semiconductors, the compensation pattern can further improve a conductivity of a PNP structure, or the compensation pattern can further reduce a leakage current of a NPN structure.
-
公开(公告)号：US11824105B2
公开(公告)日：2023-11-21
申请号：US17227450
申请日：2021-04-12
发明人： Junichi Koezuka , Yukinori Shima , Hajime Tokunaga , Toshinari Sasaki , Keisuke Murayama , Daisuke Matsubayashi
IPC分类号： H01L29/66 , H01L21/02 , H01L29/51 , H01L29/786 , H01L27/12
CPC分类号： H01L29/66969 , H01L21/022 , H01L21/02263 , H01L27/1225 , H01L29/513 , H01L29/7869 , H01L29/78609
摘要： To reduce defects in an oxide semiconductor film in a semiconductor device. To improve the electrical characteristics and the reliability of a semiconductor device including an oxide semiconductor film. In a semiconductor device including a transistor including a gate electrode formed over a substrate, a gate insulating film covering the gate electrode, a multilayer film overlapping with the gate electrode with the gate insulating film provided therebetween, and a pair of electrodes in contact with the multilayer film, a first oxide insulating film covering the transistor, and a second oxide insulating film formed over the first oxide insulating film, the multilayer film includes an oxide semiconductor film and an oxide film containing In or Ga, the first oxide insulating film is an oxide insulating film through which oxygen is permeated, and the second oxide insulating film is an oxide insulating film containing more oxygen than that in the stoichiometric composition.
-
公开(公告)号：US20230260844A1
公开(公告)日：2023-08-17
申请号：US18308213
申请日：2023-04-27
发明人： Shahaji B. MORE , Chun Hsiung Tsai
IPC分类号： H01L21/8234 , H01L29/06 , H01L29/423 , H01L29/786 , H01L29/66 , H01L21/02 , H01L29/78
CPC分类号： H01L21/823431 , H01L29/0649 , H01L29/0673 , H01L29/42392 , H01L29/78609 , H01L29/66742 , H01L29/78696 , H01L21/02603 , H01L21/02532 , H01L29/78618 , H01L21/823481 , H01L29/785 , H01L29/0665 , H01L29/66795 , H01L21/76224
摘要： The present disclosure is directed to methods for the fabrication of gate-all-around (GAA) field effect transistors (FETs) with low power consumption. The method includes depositing a first and a second epitaxial layer on a substrate and etching trench openings in the first and second epitaxial layers and the substrate. The method further includes removing, through the trench openings, portions of the first epitaxial layer to form a gap between the second epitaxial layer and the substrate and depositing, through the trench openings, a first dielectric to fill the gap and form an isolation structure. In addition, the method includes depositing a second dielectric in the trench openings to form trench isolation structures and forming a transistor structure on the second epitaxial layer.
-
公开(公告)号：US20190221674A1
公开(公告)日：2019-07-18
申请号：US16367329
申请日：2019-03-28
IPC分类号： H01L29/786 , H01L29/45 , H01L27/12 , H01L29/49 , H01L29/66
CPC分类号： H01L29/78696 , H01L27/1225 , H01L27/1255 , H01L29/45 , H01L29/4908 , H01L29/66969 , H01L29/78609 , H01L29/78648 , H01L29/7869
摘要： A transistor with favorable electrical characteristics is provided. One embodiment of the present invention is a semiconductor device including a semiconductor, a first insulator in contact with the semiconductor, a first conductor in contact with the first insulator and overlapping with the semiconductor with the first insulator positioned between the semiconductor and the first conductor, and a second conductor and a third conductor, which are in contact with the semiconductor. One or more of the first to third conductors include a region containing tungsten and one or more elements selected from silicon, carbon, germanium, tin, aluminum, and nickel.
-
-
-
-
-
-
-
-
-
搜索结果
1181 条记录 (耗时 0.022 秒)
