公开(公告)号：US20240363762A1

公开(公告)日：2024-10-31

申请号：US18769998

申请日：2024-07-11

申请人： Taiwan Semiconductor Manufacturing Company Limited

发明人： Yong-Jie Wu ,  Hui-Hsien Wei ,  Yen-Chung Ho ,  Mauricio Manfrini ,  Chia-Jung Yu ,  Chung-Te Lin ,  Pin-Cheng Hsu

IPC分类号： H01L29/786 ,  H01L29/40 ,  H01L29/417 ,  H01L29/423 ,  H01L29/66

CPC分类号： H01L29/78696 ,  H01L29/401 ,  H01L29/41733 ,  H01L29/41775 ,  H01L29/42364 ,  H01L29/42384 ,  H01L29/66742 ,  H01L29/78618 ,  H01L29/7869

摘要： A semiconductor device includes a first dielectric layer, a gate electrode embedded within the first dielectric layer, a layer stack including a gate dielectric layer, a channel layer including a semiconducting metal oxide material, and a second dielectric layer, and a source electrode and a drain electrode embedded in the second dielectric layer and contacting a respective portion of a top surface of the channel layer. A combination of the gate electrode, the gate dielectric layer, the channel layer, the source electrode, and the drain electrode forms a transistor. The total length of the periphery of a bottom surface of the channel layer that overlies the gate electrode is equal to the width of the gate electrode or twice the width of the gate electrode, and resputtering of the gate electrode material on sidewalls of the channel layer is minimized.

公开(公告)号：US20240363630A1

公开(公告)日：2024-10-31

申请号：US18770372

申请日：2024-07-11

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Kuan-Ting PAN ,  Kuo-Cheng CHIANG ,  Shi Ning JU ,  Yi-Ruei JHAN ,  Kuan-Lun CHENG ,  Chih-Hao WANG

IPC分类号： H01L27/092 ,  H01L21/02 ,  H01L21/8238 ,  H01L29/06 ,  H01L29/417 ,  H01L29/423 ,  H01L29/66 ,  H01L29/786

CPC分类号： H01L27/092 ,  H01L21/0259 ,  H01L21/823807 ,  H01L21/823878 ,  H01L29/0665 ,  H01L29/41733 ,  H01L29/42392 ,  H01L29/66742 ,  H01L29/78696

摘要： Gate isolation techniques disclosed herein form gate isolation fins to isolate metal gates of multigate devices from one another before forming the multigate devices, and in particular, before forming the metal gates of the multigate devices. An exemplary device includes a first multigate device having first source/drain features and a first metal gate that surrounds a first channel layer and a second multigate device having second source/drain features and a second metal gate that surrounds a second channel layer. A gate isolation fin, which separates the first metal gate and the second metal gate, includes a dielectric feature having a first dielectric layer having a first dielectric constant (e.g., a low-k dielectric core) and a second dielectric layer (e.g., a high-k dielectric shell) surrounding the first dielectric layer. The second dielectric layer has a second dielectric constant that is greater than the first dielectric constant.

公开(公告)号：US20240363491A1

公开(公告)日：2024-10-31

申请号：US18240675

申请日：2023-08-31

申请人： Samsung Electronics Co., Ltd.

发明人： SEUNGCHAN YUN ,  WONHYUK HONG ,  PANJAE PARK ,  KANG-ILL SEO

IPC分类号： H01L23/48 ,  H01L21/768 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/06 ,  H01L29/417 ,  H01L29/423 ,  H01L29/66 ,  H01L29/775 ,  H01L29/786

CPC分类号： H01L23/481 ,  H01L21/76898 ,  H01L21/823475 ,  H01L27/088 ,  H01L29/0673 ,  H01L29/41733 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/775 ,  H01L29/78696

摘要： Integrated circuit devices and methods of forming the same are provided. The integrated circuit devices may include a transistor comprising a source/drain region on a substrate; a backside power rail spaced apart from the source/drain region; and a power contact that is between the source/drain region and the backside power rail and electrically connects the source/drain region to the backside power rail. The substrate may be between the source/drain region and the backside power rail, and a centerline in a width direction of the source/drain region is angled with respect to a centerline in a width direction of the power contact.

公开(公告)号：US20240355891A1

公开(公告)日：2024-10-24

申请号：US18753781

申请日：2024-06-25

申请人： Intel Corporation

发明人： Leonard P. Guler ,  Shengsi Liu ,  Saurabh Acharya ,  Baofu Zhu ,  Meenakshisundaram Ramanathan ,  Charles H. Wallace ,  Ankit Kirit Lakhani

IPC分类号： H01L29/417 ,  H01L27/092 ,  H01L29/06 ,  H01L29/423 ,  H01L29/778 ,  H01L29/786

CPC分类号： H01L29/41733 ,  H01L27/092 ,  H01L29/0665 ,  H01L29/42392 ,  H01L29/778 ,  H01L29/78696

摘要： Techniques are provided herein to form semiconductor devices that include a conductive bridge between topside contacts on adjacent source or drain regions. The conductive bridge extends through a dielectric wall that separates the adjacent source or drain regions. In an example, a first semiconductor device includes a first gate structure around or otherwise on a first semiconductor region (or channel region) that extends from a first source or drain region, and a second adjacent semiconductor device includes a second gate structure around or otherwise on a second semiconductor region that extends from a second source or drain region. A conductive bridge connects a first conductive contact on a top surface of the first source or drain region with a second conductive contact on a top surface of the adjacent second source or drain region through a dielectric wall that otherwise separates the conductive contacts.

公开(公告)号：US20240355890A1

公开(公告)日：2024-10-24

申请号：US18136991

申请日：2023-04-20

申请人： Intel Corporation

发明人： Leonard P. Guler ,  Shengsi Liu ,  Saurabh Acharya ,  Baofu Zhu ,  Meenakshisundaram Ramanathan ,  Charles H. Wallace ,  Ankit Kirit Lakhani

IPC分类号： H01L29/417 ,  H01L27/092 ,  H01L29/06 ,  H01L29/423 ,  H01L29/778 ,  H01L29/786

CPC分类号： H01L29/41733 ,  H01L27/092 ,  H01L29/0665 ,  H01L29/42392 ,  H01L29/778 ,  H01L29/78696

摘要： Techniques are provided herein to form semiconductor devices that include a conductive bridge between topside contacts on adjacent source or drain regions. The conductive bridge extends through a dielectric wall that separates the adjacent source or drain regions. In an example, a first semiconductor device includes a first gate structure around or otherwise on a first semiconductor region (or channel region) that extends from a first source or drain region, and a second adjacent semiconductor device includes a second gate structure around or otherwise on a second semiconductor region that extends from a second source or drain region. A conductive bridge connects a first conductive contact on a top surface of the first source or drain region with a second conductive contact on a top surface of the adjacent second source or drain region through a dielectric wall that otherwise separates the conductive contacts.

公开(公告)号：US12127446B2

公开(公告)日：2024-10-22

申请号：US17538465

申请日：2021-11-30

申请人： LG Display Co., Ltd.

发明人： SeongPil Cho ,  JunSeuk Lee ,  YongBin Kang ,  HeeJin Jung ,  Jangdae Kim ,  Dongyup Kim ,  WonHo Son ,  Chanho Kim

IPC分类号： H10K59/123 ,  H01L27/12 ,  H01L29/417 ,  H01L29/786 ,  H10K59/121 ,  H10K59/124

CPC分类号： H10K59/123 ,  H10K59/1213 ,  H10K59/124 ,  H01L27/1225 ,  H01L29/41733 ,  H01L29/78675 ,  H01L29/7869

摘要： A display device includes a substrate including a plurality of sub-pixels, a first buffer layer on the substrate, an etch stopper on the first buffer layer, a second buffer layer covering the first buffer layer, and a first transistor on the second buffer layer. The first transistor includes a source electrode and a drain electrode overlapping the etch stopper. The etch stopper includes a hole in which at least one of the source electrode and the drain electrode is disposed. The etch stopper is spaced apart from the source electrode and the drain electrode. Therefore, it is possible to prevent moisture and impurities from penetrating into a display device by protecting a buffer layer.

公开(公告)号：US20240347105A1

公开(公告)日：2024-10-17

申请号：US18635268

申请日：2024-04-15

申请人： SEOUL NATIONAL UNIVERSITY R&DB FOUNDATION

发明人： Jae-Joon KIM ,  Munhyeon KIM

IPC分类号： G11C11/419 ,  G11C5/06 ,  H01L29/06 ,  H01L29/417 ,  H01L29/423 ,  H01L29/66 ,  H01L29/775 ,  H01L29/786 ,  H10B10/00

CPC分类号： G11C11/419 ,  G11C5/063 ,  H01L29/0673 ,  H01L29/41733 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/775 ,  H01L29/78696 ,  H10B10/125

摘要： A random access memory includes a first transistor including a first gate extending in a first direction, a second transistor disposed on a same plane as the first transistor and including a second gate extending in the first direction, a third transistor including a third gate extending in a second direction perpendicular to the first direction and formed on the first transistor, a fourth transistor including a fourth gate extending in the second direction and formed on the second transistor, a first storage node connecting the first gate of the first transistor to a drain of the third transistor and storing data, and a second storage node connecting the second gate of the second transistor to a drain of the fourth transistor and storing data.

公开(公告)号：US12119407B2

公开(公告)日：2024-10-15

申请号：US18163045

申请日：2023-02-01

申请人： Japan Display Inc.

发明人： Masashi Tsubuku ,  Michiaki Sakamoto ,  Takashi Okada ,  Toshiki Kaneko ,  Tatsuya Toda

IPC分类号： H01L29/786 ,  H01L29/417

CPC分类号： H01L29/7869 ,  H01L29/41733

摘要： A semiconductor device includes a gate electrode on a substrate, a gate insulating film on the gate electrode, an oxide semiconductor film via the gate insulating film on the gate electrode, a source electrode and a drain electrode on the oxide semiconductor film, a protective film provided on the source electrode and the drain electrode; and a conductive layer provided on the protective film and overlapped on the oxide semiconductor layer. The protective film includes a first silicon oxide film and a first silicon nitride film. The first oxide film is in contact with the oxide semiconductor layer. The gate insulating film includes a second silicon nitride film and a second silicon oxide film. The second silicon oxide film is in contact with the oxide semiconductor layer. The oxide semiconductor layer has a first region located between the source electrode and the drain electrode in a plan view.

公开(公告)号：US20240339452A1

公开(公告)日：2024-10-10

申请号：US18297996

申请日：2023-04-10

申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION

发明人： Brent A. Anderson ,  Ruilong Xie ,  Junli Wang ,  Jay William Strane ,  Albert M. Chu

IPC分类号： H01L27/092 ,  H01L21/8238 ,  H01L29/06 ,  H01L29/08 ,  H01L29/417 ,  H01L29/423 ,  H01L29/66 ,  H01L29/775 ,  H01L29/786

CPC分类号： H01L27/0922 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823871 ,  H01L21/823878 ,  H01L29/0673 ,  H01L29/0847 ,  H01L29/41733 ,  H01L29/41775 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/6656 ,  H01L29/775 ,  H01L29/78696 ,  H01L29/66545

摘要： An air pocket is located between a top S/D region and a bottom S/D region of a stacked transistor. The air pocket reduces the parasitic capacitance between the top S/D region and the bottom S/D region, reduces the capacitance between the gate and the top S/D region, and/or reduces the capacitance between the gate and the bottom S/D region. Reduction of such capacitance(s) may improve performance of the semiconductor IC device and may allow for further semiconductor IC device scaling. A semiconductor IC device may include a bottom transistor and a top transistor. The top transistor may be vertically stacked, or aligned, with respect to the bottom transistor. The air pocket is located between, and may be vertically aligned with, the top S/D region and the bottom S/D region.

公开(公告)号：US12112866B2

公开(公告)日：2024-10-08

申请号：US17392772

申请日：2021-08-03

申请人： Samsung Electronics Co., Ltd.

发明人： Yeongjun Lee ,  Joo Young Kim ,  Youngjun Yun ,  Hyun Bum Kang ,  Jong Won Chung

IPC分类号： H01B5/14 ,  C23C14/24 ,  H01B5/16 ,  H01L27/12 ,  H01L27/146 ,  H01L29/417 ,  H01L29/423 ,  H01L29/786

CPC分类号： H01B5/14 ,  C23C14/24 ,  H01B5/16 ,  H01L27/1218 ,  H01L27/1244 ,  H01L27/14678 ,  H01L29/41733 ,  H01L29/42384 ,  H01L29/78603

摘要： A stacked structure for a stretchable device includes a stretchable layer including an elastic polymer, and a conductive layer on the stretchable layer and including a metal, wherein the stretchable layer includes a first depth region and a second depth region sequentially disposed in a depth direction from a surface of the stretchable layer that is in contact with the conductive layer and the first depth region includes the metal.