Invention Publication
- Patent Title: Gate Isolation for Multigate Device
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Application No.: US18770372Application Date: 2024-07-11
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Publication No.: US20240363630A1Publication Date: 2024-10-31
- Inventor: Kuan-Ting PAN , Kuo-Cheng CHIANG , Shi Ning JU , Yi-Ruei JHAN , Kuan-Lun CHENG , Chih-Hao WANG
- Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicant Address: TW Hsin-Chu
- Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
- Current Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
- Current Assignee Address: TW Hsin-Chu
- Main IPC: H01L27/092
- IPC: H01L27/092 ; H01L21/02 ; H01L21/8238 ; H01L29/06 ; H01L29/417 ; H01L29/423 ; H01L29/66 ; H01L29/786

Abstract:
Gate isolation techniques disclosed herein form gate isolation fins to isolate metal gates of multigate devices from one another before forming the multigate devices, and in particular, before forming the metal gates of the multigate devices. An exemplary device includes a first multigate device having first source/drain features and a first metal gate that surrounds a first channel layer and a second multigate device having second source/drain features and a second metal gate that surrounds a second channel layer. A gate isolation fin, which separates the first metal gate and the second metal gate, includes a dielectric feature having a first dielectric layer having a first dielectric constant (e.g., a low-k dielectric core) and a second dielectric layer (e.g., a high-k dielectric shell) surrounding the first dielectric layer. The second dielectric layer has a second dielectric constant that is greater than the first dielectric constant.
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