公开(公告)号：US20250063792A1

公开(公告)日：2025-02-20

申请号：US18526473

申请日：2023-12-01

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Jia-Chuan YOU ,  Chia-Hao CHANG ,  Chu-Yuan HSU ,  Kuo-Cheng CHIANG ,  Chih-Hao WANG

IPC: H01L29/66 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/06 ,  H01L29/08 ,  H01L29/423 ,  H01L29/775 ,  H01L29/786

Abstract: Gate isolation processes (e.g., gate-to-source/drain contact isolation) are described herein. An exemplary contact gate isolation process may include recessing (e.g., by etching) sidewall portions of a high-k gate dielectric and gate spacers of a gate structure to form a contact gate isolation (CGI) opening that exposes sidewalls of a gate electrode of the gate structure, forming a gate isolation liner along the sidewalls of the gate electrode that partially fills the CGI opening, and forming a gate isolation layer over the gate isolation liner that fills a remainder of the CGI opening. A dielectric constant of the gate isolation liner is less than a dielectric constant of the high-k gate dielectric. A dielectric constant of the gate isolation layer is less than a dielectric constant of the high-k gate dielectric. A dielectric constant of the gate isolation layer may be less than a dielectric constant of the gate isolation layer.

公开(公告)号：US20250046718A1

公开(公告)日：2025-02-06

申请号：US18524661

申请日：2023-11-30

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Chun-Yuan CHEN ,  Huan-Chieh SU ,  Kuo-Cheng CHIANG ,  Chih-Hao WANG

IPC: H01L23/535 ,  H01L21/768 ,  H01L29/06 ,  H01L29/40 ,  H01L29/417 ,  H01L29/423 ,  H01L29/66 ,  H01L29/775

Abstract: Embodiments of the present disclosure provide a method for forming backside gate contacts and semiconductor fabricated thereof. A semiconductor device includes both signal outputs, such as source/drain contacts, and signal inputs, such as gate contacts, formed on a backside of the substrate. The backside gate contacts and backside source/drain contacts are formed in a self-aligned manner.

公开(公告)号：US20240404882A1

公开(公告)日：2024-12-05

申请号：US18674975

申请日：2024-05-27

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Sheng-Tsung WANG ,  Chia-Hao CHANG ,  Lin-Yu HUANG ,  Cheng-Chi CHUANG ,  Chih-Hao WANG

IPC: H01L21/768 ,  H01L23/522

Abstract: Embodiments of the present disclosure provide semiconductor devices having conductive features with reduced height and increased width, and methods for forming the semiconductor devices. Particularly, sacrificial self-aligned contact (SAC) layer and sacrificial metal contact etch stop layer (M-CESL) are used to form conductive features with reduced resistance. After formation of the conductive features, the sacrificial SAC and sacrificial M-CESL are removed and replaced with a low-k material to reduce capacitance in the device. As a result, performance of the device is improved.

公开(公告)号：US20240387627A1

公开(公告)日：2024-11-21

申请号：US18786484

申请日：2024-07-27

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Lung-Kun CHU ,  Mao-Lin HUANG ,  Chung-Wei HSU ,  Jia-Ni YU ,  Kuan-Lun CHENG ,  Kuo-Cheng CHIANG ,  Chih-Hao WANG

IPC: H01L29/06 ,  H01L21/8234 ,  H01L29/08

Abstract: A semiconductor device structure, along with methods of forming such, are described. The structure includes first and second dielectric features and a first semiconductor layer disposed between the first and second dielectric features. The structure further includes an isolation layer disposed between the first and second dielectric features, and the isolation layer is in contact with the first and second dielectric features. The first semiconductor layer is disposed over the isolation layer. The structure further includes a gate dielectric layer disposed over the isolation layer and a gate electrode layer disposed over the gate dielectric layer. The gate electrode layer has an end extending to a level between a first plane defined by a first surface of the first semiconductor layer and a second plane defined by a second surface opposite the first surface.

公开(公告)号：US20240363684A1

公开(公告)日：2024-10-31

申请号：US18308912

申请日：2023-04-28

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Chun-Yuan CHEN ,  Lo-Heng CHANG ,  Huan-Chieh SU ,  Chih-Hao WANG ,  Szu-Chien WU

IPC: H01L29/06 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/417 ,  H01L29/423 ,  H01L29/66 ,  H01L29/775 ,  H01L29/786

CPC classification number: H01L29/0673 ,  H01L21/823412 ,  H01L21/823418 ,  H01L27/088 ,  H01L29/41733 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/66545 ,  H01L29/775 ,  H01L29/78696

Abstract: A method for manufacturing a semiconductor structure includes forming first and second fins over a substrate. The fin includes first and second semiconductor layers alternating stacked. The method further includes forming a dummy gate structure over the first and second fins, forming first source/drain features on opposite sides of the dummy gate structures and over the first fin, forming second source/drain features on opposite sides of the dummy gate structures and over the second fin, forming a dielectric layer over and between the first and second source/drain features, replacing the dummy gate structure and the first semiconductor layers with a gate structure wrapping around the first semiconductor layers, forming first silicide features over the first source/drain features, and forming second silicide features over the second source/drain features.

公开(公告)号：US20240363444A1

公开(公告)日：2024-10-31

申请号：US18770299

申请日：2024-07-11

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Kuo-Cheng CHIANG ,  Chih-Hao WANG ,  Ching-Wei TSAI ,  Kuan-Lun CHENG

IPC: H01L21/84 ,  H01L21/8234 ,  H01L27/06 ,  H01L27/088 ,  H01L27/12

CPC classification number: H01L21/845 ,  H01L21/823412 ,  H01L21/823431 ,  H01L27/0623 ,  H01L27/0886 ,  H01L27/1207 ,  H01L27/1211

Abstract: The present disclosure relates to a semiconductor device and a manufacturing method, and more particularly to a semiconductor device with fin structures having different top surface crystal orientations and/or different materials. The present disclosure provides a semiconductor structure including n-type FinFET devices and p-type FinFET devices with different top surface crystal orientations and with fin structures having different materials. The present disclosure provides a method to fabricate a semiconductor structure including n-type FinFET devices and p-type FinFET devices with different top surface crystal orientations and different materials to achieve optimized electron transport and hole transport. The present disclosure also provides a diode structure and a bipolar junction transistor structure that includes SiGe in the fin structures.

公开(公告)号：US20240297081A1

公开(公告)日：2024-09-05

申请号：US18646878

申请日：2024-04-26

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Kuan-Ting Pan ,  Yi-Ruei JHAN ,  Chih-Hao WANG ,  Shi Ning JU ,  Kuo-Cheng CHIANG ,  Kuan-Lun CHENG

IPC: H01L21/8234 ,  H01L27/088 ,  H01L29/06 ,  H01L29/423 ,  H01L29/66 ,  H01L29/786

CPC classification number: H01L21/823468 ,  H01L21/823431 ,  H01L27/0886 ,  H01L29/0665 ,  H01L29/42392 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/6656 ,  H01L29/66795 ,  H01L29/78696

Abstract: Embodiments of the present disclosure provide a method of forming sidewall spacers by filling a trench between a hybrid fin and a semiconductor fin structure. The sidewall spacer includes two fin sidewall spacer portions connected by a gate sidewall spacer portion. The fin sidewall spacer portion has a substantially uniform profile to provide uniform protection for vertically stacked channel layers and eliminate any gaps and leaks between inner spacers and sidewall spacers.

公开(公告)号：US20240250017A1

公开(公告)日：2024-07-25

申请号：US18604557

申请日：2024-03-14

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Lin-Yu HUANG ,  Li-Zhen YU ,  Chia-Hao CHANG ,  Cheng-Chi CHUANG ,  Kuan-Lun CHENG ,  Chih-Hao WANG

IPC: H01L23/522 ,  H01L21/768 ,  H01L23/532

CPC classification number: H01L23/5222 ,  H01L21/76804 ,  H01L21/7682 ,  H01L21/76834 ,  H01L21/76843 ,  H01L23/5226 ,  H01L23/5329

Abstract: A semiconductor device structure, along with methods of forming such, are described. The semiconductor device structure includes a device, a first dielectric material disposed over the device, and an opening is formed in the first dielectric material. The semiconductor device structure further includes a conductive structure disposed in the opening, and the conductive structure includes a first sidewall. The semiconductor device structure further includes a surrounding structure disposed in the opening, and the surrounding structure surrounds the first sidewall of the conductive structure. The surrounding structure includes a first spacer layer and a second spacer layer adjacent the first spacer layer. The first spacer layer is separated from the second spacer layer by an air gap.

公开(公告)号：US20240243186A1

公开(公告)日：2024-07-18

申请号：US18155296

申请日：2023-01-17

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Chun-Fu LU ,  Lung-Kun CHU ,  Jia-Ni YU ,  Mao-Lin HUANG ,  Chung-Wei HSU ,  Kuo-Cheng CHIANG ,  Chih-Hao WANG

IPC: H01L29/66 ,  H01L21/285 ,  H01L21/306 ,  H01L29/06 ,  H01L29/423 ,  H01L29/786

CPC classification number: H01L29/66545 ,  H01L21/28575 ,  H01L21/30604 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/78696

Abstract: A method for forming a semiconductor device structure includes forming nanostructures in a first region and a second region over a substrate. The method also includes forming a gate dielectric layer surrounding the nanostructures. The method also includes forming dummy structures between the nanostructures. The method also includes forming a dielectric layer over the nanostructures. The method also includes forming a dielectric structure between the nanostructures in the first region and nanostructures in the second region. The method also includes removing the dummy structures in the first region. The method also includes depositing a first work function layer over the nanostructures. The method also includes removing the first work function layer and the dummy structures in the second region. The method also includes depositing a second work function layer over the nanostructures.

公开(公告)号：US20240113195A1

公开(公告)日：2024-04-04

申请号：US18172703

申请日：2023-02-22

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Jia-Ni YU ,  Lung-Kun CHU ,  Chun-Fu LU ,  Chung-Wei HSU ,  Mao-Lin HUANG ,  Kuo-Cheng CHIANG ,  Chih-Hao WANG

IPC: H01L29/423 ,  H01L29/06 ,  H01L29/66 ,  H01L29/775 ,  H01L29/786

CPC classification number: H01L29/42392 ,  H01L29/0642 ,  H01L29/66439 ,  H01L29/775 ,  H01L29/78696 ,  B82Y40/00 ,  H01L29/0673 ,  H01L29/66545

Abstract: Semiconductor structures and methods for forming the same are provided. The semiconductor structure includes a plurality of first nanostructures formed over a substrate, and a dielectric wall adjacent to the first nanostructures. The semiconductor structure also includes a first liner layer between the first nanostructures and the dielectric wall, and the first liner layer is in direct contact with the dielectric wall. The semiconductor structure also includes a gate structure surrounding the first nanostructures, and the first liner layer is in direct contact with a portion of the gate structure.