-
公开(公告)号：US20240349512A1
公开(公告)日：2024-10-17
申请号：US18635072
申请日：2024-04-15
发明人： Jae-Joon KIM , Munhyeon KIM
IPC分类号： H10B53/30
CPC分类号： H10B53/30
摘要： A memory using ferroelectric metal field-effect transistors includes a drain, a source, and a gate formed on a substrate, a gate contact formed on an upper portion of the gate, and a ferroelectric layer disposed between the gate contact and the gate and configured to surround the gate contact, wherein the gate, the ferroelectric layer, and the gate contact operate as a capacitor having a metal-ferroelectric layer-metal (MFM) structure.
-
公开(公告)号：US20240349477A1
公开(公告)日：2024-10-17
申请号：US18635211
申请日：2024-04-15
发明人： Jae-Joon KIM , Munhyeon KIM
IPC分类号： H10B12/00
CPC分类号： H10B12/00
摘要： A random access memory includes a first transistor including a first gate extending in a first direction, a second transistor including a second gate extending in a second direction perpendicular to the first direction and formed on an upper portion of the first transistor, and a storage node configured to connect a first gate of the first transistor to a drain of the second transistor and storing data.
-
公开(公告)号：US20240347105A1
公开(公告)日：2024-10-17
申请号：US18635268
申请日：2024-04-15
发明人： Jae-Joon KIM , Munhyeon KIM
IPC分类号： G11C11/419 , G11C5/06 , H01L29/06 , H01L29/417 , H01L29/423 , H01L29/66 , H01L29/775 , H01L29/786 , H10B10/00
CPC分类号： G11C11/419 , G11C5/063 , H01L29/0673 , H01L29/41733 , H01L29/42392 , H01L29/66439 , H01L29/775 , H01L29/78696 , H10B10/125
摘要： A random access memory includes a first transistor including a first gate extending in a first direction, a second transistor disposed on a same plane as the first transistor and including a second gate extending in the first direction, a third transistor including a third gate extending in a second direction perpendicular to the first direction and formed on the first transistor, a fourth transistor including a fourth gate extending in the second direction and formed on the second transistor, a first storage node connecting the first gate of the first transistor to a drain of the third transistor and storing data, and a second storage node connecting the second gate of the second transistor to a drain of the fourth transistor and storing data.
-
公开(公告)号：US20230153588A1
公开(公告)日：2023-05-18
申请号：US17972046
申请日：2022-10-24
发明人： Byung-Gook PARK , Munhyeon KIM
IPC分类号： G06N3/063
CPC分类号： G06N3/063
摘要： A neuromorphic device comprises a synaptic array including a plurality of word lines and bit lines and including a plurality of synaptic elements coupled to intersections of each of the word lines and the bit lines, a word line signal output unit that sequentially outputs a plurality of word line signals for activating the word lines, a signal pre-processing unit that preprocesses a spike signal to modulates the spike signal into an input signal, a weight summation unit including a plurality of weight summation circuits that respectively output a plurality of output signals obtained by applying respective weighted values stored in the synaptic array to a plurality of input signals input through the signal pre-processing unit, and a data output unit that transmits the output signals output by the weight summation unit respectively to a plurality of output neurons in response to the word line signal.
-
-
-
搜索结果
4 条记录 (耗时 0.017 秒)
