公开(公告)号：US20250071964A1

公开(公告)日：2025-02-27

申请号：US18456025

申请日：2023-08-25

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Tsung-Kai Chiu ,  Ting-Yun Wu ,  Cheng-Yin Wang ,  Szuya Liao

IPC: H10B10/00

Abstract: In an embodiment, a device includes: a first transistor including a first gate structure; a second transistor including a second gate structure, the second gate structure disposed above and coupled to the first gate structure; a third gate structure; a fourth gate structure, the fourth gate structure disposed above and coupled to the third gate structure; a gate isolation region between the first gate structure and the third gate structure, the gate isolation region disposed between the second gate structure and the fourth gate structure; and a cross-coupling contact extending beneath the gate isolation region, the first gate structure, and the third gate structure, the cross-coupling contact coupled to the first gate structure.

公开(公告)号：US20250069991A1

公开(公告)日：2025-02-27

申请号：US18454963

申请日：2023-08-24

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Ping-Wei Wang ,  Jui-Lin Chen

IPC: H01L23/48 ,  H01L29/06 ,  H01L29/417 ,  H01L29/775 ,  H01L29/786 ,  H10B10/00

Abstract: A semiconductor structure includes a first source/drain (S/D) epitaxial feature, a second S/D epitaxial feature adjacent to the first S/D epitaxial feature, an insulating structure between the first and the second S/D epitaxial features, and a shared S/D contact over top surfaces of the first and the second S/D epitaxial features. A center portion of the shared S/D contact is directly between a side surface of the first S/D epitaxial feature and a side surface of the second S/D epitaxial feature. The center portion is directly above the insulating structure. The semiconductor structure further includes a backside via penetrating through the insulating structure to directly land on a bottom surface of the center portion.

公开(公告)号：US20250069650A1

公开(公告)日：2025-02-27

申请号：US18744498

申请日：2024-06-14

Applicant: Shanghai Huali Integrated Circuit Corporation

Inventor： Pinhan CHEN ,  Gang LI

IPC: G11C11/412 ,  G11C11/419 ,  H10B10/00

Abstract: The present application discloses a three-port SRAM circuit, which is formed by adding two read ports to a six-transistor single-port SRAM circuit. Storage states of a first node and a second node of the six-transistor single-port SRAM circuit are opposite, so that a third P-type transistor with a gate terminal thereof corresponding to the first node and a fifth N-type transistor with a gate terminal thereof corresponding to the second node can be on/off synchronously. When a sixth N-type transistor and a fourth P-type transistor are both on, a port C bit line and a port B bit line can be held/discharge synchronously, so as to facilitate a system operating a peripheral circuit simultaneously when reading ports B and C at high speeds.

公开(公告)号：US20250063710A1

公开(公告)日：2025-02-20

申请号：US18449792

申请日：2023-08-15

Applicant: International Business Machines Corporation

Inventor： Min Gyu Sung ,  Julien Frougier ,  Ruilong Xie ,  Liqiao Qin

IPC: H10B10/00

Abstract: Embodiments of the invention include a semiconductor structure having a first transistor having first nanosheets as first channel regions, a second transistor having second nanosheets as second channel regions, and a third transistor having third nanosheets as third channel regions. The first, second, and third nanosheets are formed of nanosheet material, where the first nanosheets are fewer in number than the second nanosheets. The semiconductor structure includes first end portions formed of the nanosheet material between first inner spacers in the first transistor. The first end portions are opposite one another and discontinuous in the first transistor.

公开(公告)号：US20250056784A1

公开(公告)日：2025-02-13

申请号：US18448581

申请日：2023-08-11

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Jhon-Jhy LIAW

IPC: H10B10/00 ,  G11C11/412

Abstract: A memory device includes a first static random-access memory (SRAM) array having first SRAM cell groups arranged in an X-direction and a second SRAM array having second SRAM cell groups arranged in the X-direction. Each of the first SRAM cell groups includes two adjacent first SRAM cells arranged in the X-direction. Each of the first SRAM cells includes a first bit-line conductor and a first bit-line-bar conductor extending in a Y-direction. Each of the second SRAM cell groups includes two adjacent second SRAM cells arranged in the X-direction and sharing a second bit-line conductor and a second bit-line-bar conductor extending in the Y-direction. A first cell size of the first SRAM cells is larger than a second cell size of the second SRAM cells.

公开(公告)号：US12224239B2

公开(公告)日：2025-02-11

申请号：US18599049

申请日：2024-03-07

Applicant: Intel Corporation

Inventor： Smita Shridharan ,  Zheng Guo ,  Eric A. Karl ,  George Shchupak ,  Tali Kosinovsky

IPC: H01L23/528 ,  H01L23/535 ,  H01L27/092 ,  H10B10/00

Abstract: Memory bit cells having internal node jumpers are described. In an example, an integrated circuit structure includes a memory bit cell on a substrate. The memory bit cell includes first and second gate lines parallel along a second direction of the substrate. The first and second gate lines have a first pitch along a first direction of the substrate, the first direction perpendicular to the second direction. First, second and third interconnect lines are over the first and second gate lines. The first, second and third interconnect lines are parallel along the second direction of the substrate. The first, second and third interconnect lines have a second pitch along the first direction, where the second pitch is less than the first pitch. One of the first, second and third interconnect lines is an internal node jumper for the memory bit cell.

公开(公告)号：US20250048718A1

公开(公告)日：2025-02-06

申请号：US18790385

申请日：2024-07-31

Applicant: ATOMERA INCORPORATED

Inventor： DONGHUN KANG ,  MAREK HYTHA

IPC: H01L21/8238 ,  H01L29/06 ,  H01L29/423 ,  H01L29/775 ,  H01L29/786 ,  H10B10/00

Abstract: A method for making a semiconductor device may include forming a plurality of complimentary field effect transistors (CFETs). Each CFET may include an n-channel field effect transistor (NFET) and a p-channel field effect transistor (PFET) stacked in vertical relation, with each of the NFET and PFET including spaced apart source and drain regions defining respective channels therebetween. Each CFET may further include a gate overlying both of the channels, and at least one isolation layer between the NFET and the PFET. The at least one isolation layer may include a superlattice including a plurality of stacked groups of layers, with each group of layers comprising a plurality of stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions.

公开(公告)号：US20250048611A1

公开(公告)日：2025-02-06

申请号：US18365346

申请日：2023-08-04

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Yen Yu Chen ,  Ming-Yen Tsai ,  Wen-Hsing Hsieh ,  Ying-Han Chiou

IPC: H10B10/00 ,  H01L21/8238 ,  H01L29/423 ,  H01L29/66 ,  H01L29/78

Abstract: A method of forming a semiconductor structure includes forming a fin over a semiconductor substrate, forming an isolation region on sidewalls of the fin, forming a metal gate over the fin and the isolation region, etching the metal gate to form a trench through the isolation region, passivating the top portion of the semiconductor substrate exposed in the trench to form a dielectric layer at a bottom of the trench, and depositing a dielectric material in the trench to form a dielectric structure. The dielectric structure divides the metal gate into two sections.

公开(公告)号：US20250040228A1

公开(公告)日：2025-01-30

申请号：US18916723

申请日：2024-10-16

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chun-Hsien Huang ,  Yu-Tse Kuo ,  Shu-Ru Wang ,  Chien-Hung Chen ,  Li-Ping Huang ,  Chun-Yen Tseng

IPC: H01L29/423 ,  G11C5/06 ,  G11C11/412 ,  H01L29/78 ,  H10B10/00

Abstract: The present invention provides a method for forming a layout pattern of static random access memory, comprising forming a PU1 (first pull-up transistor), a PU2 (second pull-up transistor), a PD1A (first pull-down transistor), a PD1B (second pull-down transistor), a PD2A (third pull-down transistor), a PD2B (fourth pull-down transistor), a PG1A (first access transistor), a PG1B (second access transistor), a PG2A (third access transistor) and a PG2B (fourth access transistor) located on the substrate. The PD1A and the PD1B are connected in parallel with each other, the PD2A and the PD2B are connected in parallel with each other, wherein the gate structures include a first J-shaped gate structure, and the first J-shaped gate structure is an integrally formed structure.

公开(公告)号：US20250040115A1

公开(公告)日：2025-01-30

申请号：US18358981

申请日：2023-07-26

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Min Gyu Sung ,  Ruilong Xie ,  Julien Frougier

IPC: H10B10/00 ,  H01L29/06 ,  H01L29/417 ,  H01L29/423 ,  H01L29/775 ,  H01L29/786

Abstract: Embodiments of present invention provide a static random-access-memory (SRAM). The SRAM includes a first and a second pull-down (PD) transistor having respectively a first and a fourth set of nanosheets of a first width; a first and a second pass-gate (PG) transistor having respectively a second and a fifth set of nanosheets of a second width; and a first and a second pull-up (PU) transistor having respectively a third and a sixth set of nanosheets of a third width, wherein the first width is wider than the second width, the second width is wider than the third width, the first set of nanosheets is substantially aligned with the second set of nanosheets at one side of the first and second sets of nanosheets, and the fourth set of nanosheets is substantially aligned with the fifth set of nanosheets at one side of the fourth and fifth sets of nanosheets.