公开(公告)号：US11973032B2

公开(公告)日：2024-04-30

申请号：US18119225

申请日：2023-03-08

Applicant: Intel Corporation

Inventor： Smita Shridharan ,  Zheng Guo ,  Eric A. Karl ,  George Shchupak ,  Tali Kosinovsky

IPC: H01L23/528 ,  H01L23/535 ,  H01L27/092 ,  H10B10/00

CPC classification number: H01L23/528 ,  H01L23/535 ,  H01L27/0924 ,  H10B10/12

Abstract: Memory bit cells having internal node jumpers are described. In an example, an integrated circuit structure includes a memory bit cell on a substrate. The memory bit cell includes first and second gate lines parallel along a second direction of the substrate. The first and second gate lines have a first pitch along a first direction of the substrate, the first direction perpendicular to the second direction. First, second and third interconnect lines are over the first and second gate lines. The first, second and third interconnect lines are parallel along the second direction of the substrate. The first, second and third interconnect lines have a second pitch along the first direction, where the second pitch is less than the first pitch. One of the first, second and third interconnect lines is an internal node jumper for the memory bit cell.

公开(公告)号：US20230209799A1

公开(公告)日：2023-06-29

申请号：US17560927

申请日：2021-12-23

Applicant: Intel Corporation

Inventor： Clifford Ong ,  Dan Lavric ,  Leonard Guler ,  YenTing Chiu ,  Smita Shridharan ,  Zheng Guo ,  Eric A. Karl ,  Tahir Ghani

IPC: H01L27/11 ,  H01L29/49 ,  H01L29/06 ,  H01L29/423 ,  H01L29/78 ,  H01L29/786 ,  H01L29/66

CPC classification number: H01L27/1108 ,  H01L29/4908 ,  H01L29/0665 ,  H01L29/42392 ,  H01L29/78391 ,  H01L29/78696 ,  H01L29/6684 ,  H01L29/66742

Abstract: Integrated circuit (IC) static random-access memory (SRAM) comprising pass-gate transistors and pull-down transistors having different threshold voltages (Vt). A pass-gate transistor with a higher Vt than the pull-down transistor, may reduce read instability of a bit-cell, and/or reduce overhead associated with read assist circuitry coupled to the bit-cell. In some examples, a different amount of a dipole dopant source material is deposited as part of the gate insulator for the pull-down transistor than for the pass-gate transistor, reducing the Vt of the pull-down transistor accordingly. In some examples, an N-dipole dopant source material is removed from the pass-gate transistor prior to a drive/activation anneal is performed. After drive/activation, the N-dipole dopant source material may be removed from the pull-down transistor and a same gate metal deposited over both the pass-gate and pull-down transistors.

公开(公告)号：US11205616B2

公开(公告)日：2021-12-21

申请号：US16604807

申请日：2017-06-20

Applicant: Intel Corporation

Inventor： Smita Shridharan ,  Zheng Guo ,  Eric A. Karl ,  George Shchupak ,  Tali Kosinovsky

IPC: H01L23/528 ,  H01L23/535 ,  H01L27/092 ,  H01L27/11

Abstract: Memory bit cells having internal node jumpers are described. In an example, an integrated circuit structure includes a memory bit cell on a substrate. The memory bit cell includes first and second gate lines parallel along a second direction of the substrate. The first and second gate lines have a first pitch along a first direction of the substrate, the first direction perpendicular to the second direction. First, second and third interconnect lines are over the first and second gate lines. The first, second and third interconnect lines are parallel along the second direction of the substrate. The first, second and third interconnect lines have a second pitch along the first direction, where the second pitch is less than the first pitch. One of the first, second and third interconnect lines is an internal node jumper for the memory bit cell.

公开(公告)号：US12224239B2

公开(公告)日：2025-02-11

申请号：US18599049

申请日：2024-03-07

Applicant: Intel Corporation

Inventor： Smita Shridharan ,  Zheng Guo ,  Eric A. Karl ,  George Shchupak ,  Tali Kosinovsky

IPC: H01L23/528 ,  H01L23/535 ,  H01L27/092 ,  H10B10/00

Abstract: Memory bit cells having internal node jumpers are described. In an example, an integrated circuit structure includes a memory bit cell on a substrate. The memory bit cell includes first and second gate lines parallel along a second direction of the substrate. The first and second gate lines have a first pitch along a first direction of the substrate, the first direction perpendicular to the second direction. First, second and third interconnect lines are over the first and second gate lines. The first, second and third interconnect lines are parallel along the second direction of the substrate. The first, second and third interconnect lines have a second pitch along the first direction, where the second pitch is less than the first pitch. One of the first, second and third interconnect lines is an internal node jumper for the memory bit cell.

公开(公告)号：US20230320057A1

公开(公告)日：2023-10-05

申请号：US17711875

申请日：2022-04-01

Applicant: Intel Corporation

Inventor： Clifford Ong ,  Leonard Guler ,  Mohit Haran ,  Smita Shridharan ,  Reken Patel ,  Charles Wallace ,  Chanaka Munasinghe ,  Pratik Patel

IPC: H01L27/11 ,  H01L27/02 ,  G11C11/412 ,  H01L21/768 ,  H01L23/522 ,  H01L29/423

CPC classification number: H01L27/1104 ,  H01L27/0207 ,  G11C11/412 ,  H01L21/76877 ,  H01L23/5226 ,  H01L29/42392

Abstract: Integrated circuit (IC) devices include transistors with gate, source and drain contact metallization, some of which are jumpered together by a metallization that is recessed below a height of other metallization that is not jumpered. The jumper metallization may provide a local interconnect between terminals of one transistor or adjacent transistors, for example between a gate of one transistor and a source/drain of another transistor. The jumper metallization may not induce the same pitch constraints faced by interconnect line metallization levels employed for more general interconnection. In some examples, a static random-access memory (SRAM) bit-cell includes a jumper metallization joining two transistors of the cell to reduce cell height for a given feature patterning capability.

公开(公告)号：US20230209797A1

公开(公告)日：2023-06-29

申请号：US17560779

申请日：2021-12-23

Applicant: Intel Corporation

Inventor： Clifford Ong ,  Leonard Guler ,  Smita Shridharan ,  Zheng Guo ,  Eric Karl ,  Tahir Ghani

IPC: H01L27/11

CPC classification number: H01L27/1108

Abstract: Integrated circuit (IC) static random-access memory (SRAM) comprising colinear pass-gate transistors and pull-down transistors having different nanoribbon widths. A narrower ribbon width within the pass-gate transistor, relative to the pull-down transistor, may reduce read instability of a bit-cell, and/or reduce overhead associated with read assist circuitry coupled to the bit-cell. In some examples, a transition between narrower and width ribbon widths is symmetrical about a centerline shared by ribbons of both the access and pull-down transistors. In some examples, the ribbon width transition is positioned within an impurity-doped semiconductor region shared by the access and pull-down transistors and may be located under a terminal contact metallization. In some examples, the impurity-doped semiconductor regions surrounding the ribbons of differing width also have differing widths.

公开(公告)号：US11640939B2

公开(公告)日：2023-05-02

申请号：US17524665

申请日：2021-11-11

Applicant: Intel Corporation

Inventor： Smita Shridharan ,  Zheng Guo ,  Eric A. Karl ,  George Shchupak ,  Tali Kosinovsky

IPC: H01L23/528 ,  H01L23/535 ,  H01L27/092 ,  H01L27/11

Abstract: Memory bit cells having internal node jumpers are described. In an example, an integrated circuit structure includes a memory bit cell on a substrate. The memory bit cell includes first and second gate lines parallel along a second direction of the substrate. The first and second gate lines have a first pitch along a first direction of the substrate, the first direction perpendicular to the second direction. First, second and third interconnect lines are over the first and second gate lines. The first, second and third interconnect lines are parallel along the second direction of the substrate. The first, second and third interconnect lines have a second pitch along the first direction, where the second pitch is less than the first pitch. One of the first, second and third interconnect lines is an internal node jumper for the memory bit cell.