Invention Publication
- Patent Title: RECESSED TRANSISTOR TERMINAL VIA JUMPERS
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Application No.: US17711875Application Date: 2022-04-01
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Publication No.: US20230320057A1Publication Date: 2023-10-05
- Inventor: Clifford Ong , Leonard Guler , Mohit Haran , Smita Shridharan , Reken Patel , Charles Wallace , Chanaka Munasinghe , Pratik Patel
- Applicant: Intel Corporation
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Main IPC: H01L27/11
- IPC: H01L27/11 ; H01L27/02 ; G11C11/412 ; H01L21/768 ; H01L23/522 ; H01L29/423

Abstract:
Integrated circuit (IC) devices include transistors with gate, source and drain contact metallization, some of which are jumpered together by a metallization that is recessed below a height of other metallization that is not jumpered. The jumper metallization may provide a local interconnect between terminals of one transistor or adjacent transistors, for example between a gate of one transistor and a source/drain of another transistor. The jumper metallization may not induce the same pitch constraints faced by interconnect line metallization levels employed for more general interconnection. In some examples, a static random-access memory (SRAM) bit-cell includes a jumper metallization joining two transistors of the cell to reduce cell height for a given feature patterning capability.
Information query
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