公开(公告)号：US20240365526A1

公开(公告)日：2024-10-31

申请号：US18768467

申请日：2024-07-10

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Jhon Jhy Liaw

IPC: H10B10/00 ,  H01L21/8238 ,  H01L23/522 ,  H01L23/528 ,  H01L27/02 ,  H01L29/423 ,  H01L29/49 ,  H01L29/78

CPC classification number: H10B10/12 ,  H01L21/823821 ,  H01L21/823828 ,  H01L21/823857 ,  H01L21/823871 ,  H01L23/5226 ,  H01L23/528 ,  H01L27/0207 ,  H01L29/42364 ,  H01L29/4966 ,  H01L29/7851

Abstract: A semiconductor device includes a first Static Random Access Memory (SRAM) array including a first SRAM cell and a second SRAM array including a second SRAM cell. The first SRAM cell includes a first pull-down (PD) device including a single fin N-type FinFET. The single fin N-type FinFET includes a first gate dielectric having a first thickness. The second SRAM cell includes a second PD device including a multiple fin N-type FinFET. The multiple fin N-type FinFET includes a second gate dielectric having a second thickness. The first thickness is greater than the second thickness.

公开(公告)号：US20240332399A1

公开(公告)日：2024-10-03

申请号：US18732393

申请日：2024-06-03

Applicant: Intel Corporation

Inventor： Tahir GHANI ,  Byron HO ,  Michael L. HATTENDORF ,  Christopher P. AUTH

IPC: H01L29/66 ,  H01L21/02 ,  H01L21/033 ,  H01L21/28 ,  H01L21/285 ,  H01L21/308 ,  H01L21/311 ,  H01L21/762 ,  H01L21/768 ,  H01L21/8234 ,  H01L21/8238 ,  H01L23/00 ,  H01L23/522 ,  H01L23/528 ,  H01L23/532 ,  H01L27/02 ,  H01L27/088 ,  H01L27/092 ,  H01L29/06 ,  H01L29/08 ,  H01L29/165 ,  H01L29/167 ,  H01L29/417 ,  H01L29/51 ,  H01L29/78 ,  H10B10/00

CPC classification number: H01L29/66545 ,  H01L21/02532 ,  H01L21/02636 ,  H01L21/0337 ,  H01L21/28247 ,  H01L21/28518 ,  H01L21/28568 ,  H01L21/3086 ,  H01L21/31105 ,  H01L21/31144 ,  H01L21/76224 ,  H01L21/76232 ,  H01L21/76801 ,  H01L21/76802 ,  H01L21/76816 ,  H01L21/76834 ,  H01L21/76846 ,  H01L21/76849 ,  H01L21/76877 ,  H01L21/76897 ,  H01L21/823431 ,  H01L21/823481 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/823828 ,  H01L21/823842 ,  H01L21/823857 ,  H01L21/823871 ,  H01L21/823878 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/5283 ,  H01L23/53209 ,  H01L23/53238 ,  H01L23/53266 ,  H01L23/5329 ,  H01L27/0207 ,  H01L27/0886 ,  H01L27/0922 ,  H01L27/0924 ,  H01L28/20 ,  H01L28/24 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/165 ,  H01L29/167 ,  H01L29/41783 ,  H01L29/41791 ,  H01L29/516 ,  H01L29/6653 ,  H01L29/6656 ,  H01L29/66636 ,  H01L29/66795 ,  H01L29/66818 ,  H01L29/7843 ,  H01L29/7845 ,  H01L29/7846 ,  H01L29/7848 ,  H01L29/785 ,  H01L29/7851 ,  H01L29/7854 ,  H10B10/12 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/0332 ,  H01L21/76883 ,  H01L21/76885 ,  H01L21/823437 ,  H01L21/823475 ,  H01L24/16 ,  H01L24/32 ,  H01L24/73 ,  H01L29/665 ,  H01L29/7842 ,  H01L29/7853 ,  H01L2224/16227 ,  H01L2224/32225 ,  H01L2224/73204

Abstract: Embodiments of the disclosure are in the field of advanced integrated circuit structure fabrication and, in particular, 10 nanometer node and smaller integrated circuit structure fabrication and the resulting structures. In an example, a method includes forming a plurality of fins and forming a plurality of gate structures over the plurality of fins. A dielectric material structure is formed between adjacent ones of the plurality of gate structures. A portion of a first of the plurality of gate structures is removed to expose a first portion of each of the plurality of fins, and a portion of a second of the plurality of gate structures is removed to expose a second portion of each of the plurality of fins. The exposed first portion of each of the plurality of fins is removed, but the exposed second portion of each of the plurality of fins is not removed.

公开(公告)号：US20240332390A1

公开(公告)日：2024-10-03

申请号：US18736647

申请日：2024-06-07

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Bonyeop Kim ,  Taehyung Kim ,  Sangshin Han ,  Sangyeop Baeck

IPC: H01L29/423 ,  H01L27/092 ,  H01L29/06 ,  H10B10/00

CPC classification number: H01L29/42392 ,  H01L27/0924 ,  H01L29/0673 ,  H10B10/12

Abstract: An integrated circuit includes: a memory cell block including a plurality of bitcells; and an input and output (I/O) block including a plurality of gate-all-around (GAA) transistors connected to the bitcells, wherein the I/O block includes a plurality of active regions disposed separately from one another in a first direction, each of which extends in a second direction that is vertical to the first direction, and in which the GAA transistors are formed, a plurality of power rails disposed separately from one another in the first direction, and configured to provide power to the GAA transistors, and a plurality of signal lines disposed between the power rails, and configured to provide signals to the GAA transistors, a first number of bitcells among the bitcells are connected to the GAA transistors formed in a second number of active regions among the active regions, and the second number is twice the first number.

公开(公告)号：US12106799B2

公开(公告)日：2024-10-01

申请号：US17805744

申请日：2022-06-07

Applicant: CHANGXIN MEMORY TECHNOLOGIES, INC.

Inventor： Tzung-Han Lee ,  Chih-Cheng Liu

IPC: G11C11/417 ,  G11C11/412 ,  H10B10/00

CPC classification number: G11C11/417 ,  G11C11/412 ,  H10B10/12

Abstract: The present disclosure relates to a method of forming a sense amplifier and a layout structure of a sense amplifier. The method includes: providing a first active region pattern layer, the first active region pattern layer includes a bridge pattern, and a first active region pattern region and a second active region pattern region; the first active region pattern region includes a first active region pattern for defining a first pull-down transistor of a first memory cell structure; the second active region pattern region includes a first symmetrical active region pattern for defining a second pull-down transistor of a second memory cell structure; and the first active region pattern and the first symmetrical active region pattern are adjacent to each other and connected through the bridge pattern, a source of the first pull-down transistor and a source of the second pull-down transistor are electrically connected through the bridge pattern.

公开(公告)号：US20240321345A1

公开(公告)日：2024-09-26

申请号：US18672090

申请日：2024-05-23

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Yi-Hsun Chiu ,  Chia-En Huang

IPC: G11C11/412 ,  G11C11/417 ,  H10B10/00

CPC classification number: G11C11/412 ,  G11C11/417 ,  H10B10/12

Abstract: A semiconductor structure includes a substrate having a frontside and a backside; a static random-access memory (SRAM) circuit having SRAM bit cells formed on the frontside of the substrate, wherein each of the SRAM bit cells including two inverters cross-coupled together, and a first and second pass gates coupled to the two inverters; a first bit-line disposed on the frontside of the substrate and connected to the first pass gate; and a second bit-line disposed on the backside of the substrate and connected to the second pass gate.

公开(公告)号：US12101922B2

公开(公告)日：2024-09-24

申请号：US18340900

申请日：2023-06-26

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Te-Hsin Chiu ,  Jiann-Tyng Tzeng ,  Shih-Wei Peng ,  Wei-An Lai

IPC: H10B10/00 ,  G11C5/02 ,  G11C11/412 ,  H01L27/092

CPC classification number: H10B10/12 ,  G11C5/025 ,  G11C11/412 ,  H01L27/092

Abstract: A memory device is provided. The memory device includes first and second pull-up transistors. The first pull-up transistor is disposed over a semiconductor substrate, and including a first gate structure and two first source/drain structures at opposite sides of the first gate structure. The second pull-up transistor is laterally spaced apart from the first pull-up transistor, and including a second gate structure and two second source/drain structures at opposite sides of the second gate structure. The first and second gate structures extend along a first direction and laterally spaced apart from each other along a second direction intersected with the first direction. The first gate structure further extends along a sidewall of one of the second source/drain structures, and the second gate structure further extends along a sidewall of one of the first source/drain structures.

公开(公告)号：US12100436B2

公开(公告)日：2024-09-24

申请号：US18321552

申请日：2023-05-22

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Hidehiro Fujiwara ,  Hsien-Yu Pan ,  Chih-Yu Lin ,  Yen-Huei Chen ,  Wei-Chang Zhao

IPC: G11C16/04 ,  G11C11/412 ,  G11C11/419 ,  H01L27/02 ,  H10B10/00

CPC classification number: G11C11/419 ,  G11C11/412 ,  H01L27/0207 ,  H10B10/12

Abstract: A memory cell includes a write port and a read port. The write port includes two cross-coupled inverters that form a storage unit. The cross-coupled inverters are connected between a first power source signal line and a second power source signal line. The write port also includes a first local interconnect line in an interconnect layer that is connected to the second power source signal line. The read port includes a transistor that is connected to the storage unit in the write port and to the second power source signal line, and a second local interconnect line in the interconnect layer that is connected to the second power source signal line. The second local interconnect line in the read port is separate from the first local interconnect line in the write port.

公开(公告)号：US12094529B2

公开(公告)日：2024-09-17

申请号：US18354824

申请日：2023-07-19

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Yangsyu Lin ,  Po-Sheng Wang ,  Cheng Hung Lee ,  Jonathan Tsung-Yung Chang

IPC: G11C11/419 ,  G11C11/412 ,  H10B10/00

CPC classification number: G11C11/419 ,  G11C11/412 ,  H10B10/12 ,  H10B10/18

Abstract: A memory device includes a memory array having a plurality of memory cells arranged along a plurality of rows extending in a row direction and a plurality of columns extending in a column direction. The memory array also includes a plurality of write assist cells connected to the plurality of memory cells. At least one write assist cell of the plurality of write assist cells is in each of the plurality of columns and connected to respective ones of the plurality of memory cells in a same column.

公开(公告)号：US20240306358A1

公开(公告)日：2024-09-12

申请号：US18364716

申请日：2023-08-03

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Ping-Wei Wang ,  Feng-Ming Chang ,  Jui-Lin Chen

IPC: H10B10/00 ,  G11C11/412 ,  G11C11/419 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/06 ,  H01L29/423 ,  H01L29/66 ,  H01L29/775 ,  H01L29/786

CPC classification number: H10B10/12 ,  G11C11/412 ,  G11C11/419 ,  H01L21/823807 ,  H01L27/092 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/66545 ,  H01L29/775 ,  H01L29/78696

Abstract: A memory cell includes a first active region providing a plurality of first nano-structures for a write-port pass-gate transistor, a second active region providing a plurality of second nano-structures for a write-port pull-up transistor, and a third active region providing a plurality of third nano-structures for a read-port pull-down transistor. The first active region has a first width, the second active region has a second width, and the third active region having a third width. The third width is larger than the first width, and the first width is larger than the second width.

公开(公告)号：US20240284651A1

公开(公告)日：2024-08-22

申请号：US18123992

申请日：2023-03-21

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chia-Chen Sun

IPC: H10B10/00

CPC classification number: H10B10/12

Abstract: A method for fabricating a static random access memory (SRAM) includes the steps of forming a first fin-shaped structure for a first pull-down (PD) transistor on a substrate, forming a second fin-shaped structure for a second PD transistor on the substrate, forming a third fin-shaped structure for a first pass gate (PG) transistor on the substrate, and forming a fourth fin-shaped structure for a second PG transistor on the substrate. Preferably, the first fin-shaped structure and the second fin-shaped structure include a first recess therebetween and the third fin-shaped structure and the fourth fin-shaped structure include no recess therebetween.