公开(公告)号：US11980015B2

公开(公告)日：2024-05-07

申请号：US17883910

申请日：2022-08-09

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Fang Chen ,  Kuo-Chiang Ting ,  Jhon Jhy Liaw ,  Min-Chang Liang

IPC分类号： H10B10/00 ,  G11C11/412 ,  G11C11/417 ,  H01L21/8238 ,  H01L23/522 ,  H01L23/528 ,  H01L27/088 ,  H01L49/02 ,  H03K19/20 ,  H10B43/27

CPC分类号： H10B10/12 ,  G11C11/412 ,  G11C11/417 ,  H01L21/823821 ,  H01L23/5226 ,  H01L23/528 ,  H01L27/0886 ,  H01L28/00 ,  H03K19/20 ,  H10B10/18 ,  H10B43/27

摘要： An embodiment is an integrated circuit structure including a static random access memory (SRAM) cell having a first number of semiconductor fins, the SRAM cell having a first boundary and a second boundary parallel to each other, and a third boundary and a fourth boundary parallel to each other, the SRAM cell having a first cell height as measured from the third boundary to the fourth boundary, and a logic cell having the first number of semiconductor fins and the first cell height.

公开(公告)号：US11942145B2

公开(公告)日：2024-03-26

申请号：US17662364

申请日：2022-05-06

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Chih-Chuan Yang ,  Jui-Wen Chang ,  Feng-Ming Chang ,  Kian-Long Lim ,  Kuo-Hsiu Hsu ,  Lien Jung Hung ,  Ping-Wei Wang

IPC分类号： G11C5/06 ,  G11C11/417 ,  H01L29/423 ,  H10B10/00

CPC分类号： G11C11/417 ,  H01L29/42392 ,  H10B10/125

摘要： The present disclosure describes a method for memory cell placement. The method can include placing a memory cell region in a layout area and placing a well pick-up region and a first power supply routing region along a first side of the memory cell region. The method also includes placing a second power supply routing region and a bitline jumper routing region along a second side of the memory cell region, where the second side is on an opposite side to that of the first side. The method further includes placing a device region along the second side of the memory cell region, where the bitline jumper routing region is between the second power supply routing region and the device region.

公开(公告)号：US11900994B2

公开(公告)日：2024-02-13

申请号：US17883998

申请日：2022-08-09

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Atuk Katoch

IPC分类号： G11C5/14 ,  G11C11/417 ,  H10B10/00

CPC分类号： G11C11/417 ,  G11C5/148 ,  H10B10/12

摘要： A memory device including memory cells and edge cells is described. In one example, the memory device includes: an array of memory cells used for data storage; a plurality of first edge cells not used for data storage; and a plurality of second edge cells not used for data storage. The plurality of first edge cells and the plurality of second edge cells are arranged respectively at two opposite sides of the array of memory cells. At least one edge cell, among the plurality of first edge cells and the plurality of second edge cells, comprises a circuit configured for controlling the array of memory cells to enter or exit a power down mode.

公开(公告)号：US11805635B2

公开(公告)日：2023-10-31

申请号：US16992265

申请日：2020-08-13

申请人： Kioxia Corporation

发明人： Hiroaki Yamamoto ,  Shinichi Asou ,  Kenichi Kawabata ,  Haruyuki Miyata ,  Takahiro Shimokawa ,  Takaco Umezawa ,  Syunsuke Sasaki

IPC分类号： H10B10/00 ,  G11C11/417 ,  G11C11/412

CPC分类号： H10B10/12 ,  G11C11/412 ,  G11C11/417 ,  H10B10/18

摘要： According to one embodiment, a semiconductor memory device includes, on a substrate, a memory region and a peripheral circuit region in which an MOS transistor is formed. The MOS transistor includes a drain region and a source region disposed in a first direction parallel to a surface of the substrate. On a surface of the drain region, a drain electrode is formed to be connected with a contact plug. Further, on a surface of the source region, a source electrode is formed to be connected with a contact plug. When viewed in the first direction, the drain electrode has a region that does not overlap with the source electrode, and the source electrode has a region that does not overlap with the drain electrode.

公开(公告)号：US11798634B2

公开(公告)日：2023-10-24

申请号：US17675622

申请日：2022-02-18

申请人： Micron Technology, Inc.

发明人： Ki-Jun Nam ,  Takamasa Suzuki ,  Yantao Ma ,  Yasushi Matsubara

IPC分类号： G11C5/14 ,  G11C16/30 ,  G11C16/12 ,  G11C7/20 ,  G11C16/04 ,  G11C16/32 ,  G11C11/4074 ,  G11C11/417

CPC分类号： G11C16/30 ,  G11C5/144 ,  G11C5/147 ,  G11C7/20 ,  G11C11/4074 ,  G11C11/417 ,  G11C16/045 ,  G11C16/12 ,  G11C16/32

摘要： Methods, systems, and devices for sequential voltage control for a memory device are described. A memory device may have various voltage sources that support different voltage levels used in various operations of the memory device. Voltage sources of a memory device may be disabled under some circumstances, such as when the memory device is idled, or operated in a low-power or powered-down mode, among other circumstances. In accordance with examples as disclosed herein, voltage sources of a memory device or memory die may be sequentially enabled or sequentially disabled. For example, voltage sources may be enabled in an order from voltage sources having relatively higher nominal voltages to voltage sources having relatively lower voltages, or disabled in an order from voltage sources having relatively lower nominal voltages to voltage sources having relatively higher voltages.

公开(公告)号：US20230326492A1

公开(公告)日：2023-10-12

申请号：US18328836

申请日：2023-06-05

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Sanjeev Kumar Jain

IPC分类号： G11C5/14 ,  G11C11/417

CPC分类号： G11C5/148 ,  G11C11/417

摘要： Systems and methods are provided for controlling power down of an integrated dual rail memory circuit. The power down system is configured to power down the power rail for input and logic components (VDD) while maintaining power to the power rail for the memory cells (VDDM). The power down system includes two voltage rails, a clock generator, and a power detector for detecting the power on VDD. The power detector generates an isolated power signal when voltage on VDD is below a voltage threshold. The isolated power signal is configured to disable the clock generator and thus reduce dynamic power as the read/write cycle is not triggered during power down.

公开(公告)号：US11769550B2

公开(公告)日：2023-09-26

申请号：US17736220

申请日：2022-05-04

申请人： Zeno Semiconductor, Inc.

发明人： Benjamin S. Louie ,  Yuniarto Widjaja

IPC分类号： G11C11/34 ,  G11C11/417 ,  G11C5/14 ,  G11C11/412

CPC分类号： G11C11/417 ,  G11C5/147 ,  G11C5/148 ,  G11C11/412

摘要： Methods, devices, arrays and systems for reducing standby power for a floating body memory array. One method includes counting bits of data before data enters the array, wherein the counting includes counting at least one of: a total number of bits at state 1 and a total number of all bits; a total number of bits at state 0 and the total number of all bits; or the total number of bits at state 1 and the total number of bits at state 0. This method further includes detecting whether the total number of bits at state 1 is greater than the total number of bits at state 0; setting an inversion bit when the total number of bits at state 1 is greater than the total number of bits at state 0; and inverting contents of all the bits of data before writing the bits of data to the memory array when the inversion bit has been set.

公开(公告)号：US20230282273A1

公开(公告)日：2023-09-07

申请号：US18169455

申请日：2023-02-15

申请人： RENESAS ELECTRONICS CORPORATION

发明人： Shinji TANAKA ,  Daiki KITAGATA

IPC分类号： G11C11/417 ,  G11C11/412

CPC分类号： G11C11/417 ,  G11C11/412 ,  G06F7/5443

摘要： In the semiconductor device according to an embodiment, a memory cell is controlled such that, for the part whose output value can be fixed based on the value stored in the memory cell without performing the information processing, the operation processing is stopped so as to stop the charging and discharging to and from the data line, and for the part whose output value needs to be fixed by performing the information processing, the information processing accompanied by charging and discharging to and from the data line is appropriately performed.

公开(公告)号：US20230275018A1

公开(公告)日：2023-08-31

申请号：US17832584

申请日：2022-06-04

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

发明人： Chia-Tien Wu ,  Wei-Chen Chu ,  Yu-Chieh Liao ,  Hsin-Ping Chen

IPC分类号： H01L23/522 ,  H01L21/768 ,  H01L23/528 ,  H01L23/532 ,  H01L27/11 ,  G11C11/417 ,  G11C11/412

CPC分类号： H01L23/5226 ,  H01L21/76877 ,  H01L21/76816 ,  H01L23/528 ,  H01L21/76831 ,  H01L23/53252 ,  H01L27/1104 ,  G11C11/417 ,  G11C11/412

摘要： The present disclosure provides a method of fabricating a semiconductor device. The method includes forming a first interconnect layer over a substrate, the first interconnect layer including a first conductive feature and a second conductive feature, forming a patterned mask on the first interconnect layer, one or more openings in the patterned mask overlaying the second conductive feature, recessing the second conductive feature through the one or more openings in the patterned mask, and forming a second interconnect layer over the first interconnect layer. The second interconnect layer includes a first via in contact with the first conductive feature and a second via in contact with the second conductive feature.

公开(公告)号：US20230260569A1

公开(公告)日：2023-08-17

申请号：US17670384

申请日：2022-02-11

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

发明人： Hidehiro FUJIWARA ,  Haruki MORI ,  Wei-Chang ZHAO

IPC分类号： G11C11/417 ,  G11C11/412 ,  G06F7/544

CPC分类号： G11C11/417 ,  G11C11/412 ,  G06F7/5443

摘要： A memory device has a memory array of a plurality of memory cells arranged in a plurality of columns and a plurality of rows. The memory cells in each of the plurality of columns include first memory cells and second memory cells alternately arranged along a column direction of the plurality of columns. A first computation circuit is coupled to the first memory cells in each of the plurality of columns, and is configured to generate first output data corresponding to a first computation performed on first weight data stored in the first memory cells. A second computation circuit is coupled to the second memory cells in each of the plurality of columns, and is configured to generate second output data corresponding to a second computation performed on second weight data stored in the second memory cells.