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    Drift compensation for codewords in memory
    1.
    发明授权
    Drift compensation for codewords in memory 有权

    公开(公告)号：US12027212B2

    公开(公告)日：2024-07-02

    申请号：US17948556

    申请日：2022-09-20

    Applicant: Micron Technology, Inc.

    Inventor： Marco Sforzin ,  Paolo Amato ,  Luca Barletta ,  Marco Pietro Ferrari ,  Antonino Favano

    IPC: G11C16/10 ,  G11C16/12 ,  G11C16/34

    CPC classification number: G11C16/102 ,  G11C16/12 ,  G11C16/3404

    Abstract: The present disclosure includes apparatuses, methods, and systems for drift compensation for codewords in memory. An embodiment includes a memory device having an array of memory cells, and circuitry to sense a codeword stored in the array, determine a threshold voltage value of each cell of the codeword, sort the threshold voltage values, determine a second derivative value of a cell metric for a number of the cells of the codeword based on the threshold voltage value of that respective cell, the threshold voltage value immediately preceding the threshold voltage value of that respective cell in the sorted values, and a value proportional to a total quantity of the cells of the codeword, determine the cell metric for which the determined second derivative value has a greatest value, input the determined cell metric to a Pearson detector, and determine originally programmed data of the codeword using the Pearson detector.

    INTEGRATED FLAG BYTE READ DURING FAILED BYTE COUNT READ COMPENSATION IN A MEMORY DEVICE
    4.
    发明公开
    INTEGRATED FLAG BYTE READ DURING FAILED BYTE COUNT READ COMPENSATION IN A MEMORY DEVICE 审中-公开

    公开(公告)号：US20240071534A1

    公开(公告)日：2024-02-29

    申请号：US18237309

    申请日：2023-08-23

    Applicant: Micron Technology, Inc.

    Inventor： Nagendra Prasad Ganesh Rao

    IPC: G11C16/34 ,  G11C16/12 ,  G11C16/26

    CPC classification number: G11C16/3495 ,  G11C16/12 ,  G11C16/26

    Abstract: Control logic in a memory device receives a request to perform a read operation to read data from a memory array of a memory device, the request comprising an indication of a segment of the memory array where the data is stored, initiates a failed byte count read operation on the segment of the memory array to determine a failed byte count, and reads metadata stored in a flag byte corresponding to the segment of the memory array concurrently with the failed byte count read operation. The control logic further configures one or more parameters associated with the read operation based on the failed byte count and at least a portion of the metadata read from the flag byte.

    DRIFT COMPENSATION FOR CODEWORDS IN MEMORY
    5.
    发明公开
    DRIFT COMPENSATION FOR CODEWORDS IN MEMORY 审中-公开

    公开(公告)号：US20240071511A1

    公开(公告)日：2024-02-29

    申请号：US17948556

    申请日：2022-09-20

    Applicant: Micron Technology, Inc.

    Inventor： Marco Sforzin ,  Paolo Amato ,  Luca Barletta ,  Marco Pietro Ferrari ,  Antonino Favano

    IPC: G11C16/10 ,  G11C16/12 ,  G11C16/34

    CPC classification number: G11C16/102 ,  G11C16/12 ,  G11C16/3404

    Abstract: The present disclosure includes apparatuses, methods, and systems for drift compensation for codewords in memory. An embodiment includes a memory device having an array of memory cells, and circuitry to sense a codeword stored in the array, determine a threshold voltage value of each cell of the codeword, sort the threshold voltage values, determine a second derivative value of a cell metric for a number of the cells of the codeword based on the threshold voltage value of that respective cell, the threshold voltage value immediately preceding the threshold voltage value of that respective cell in the sorted values, and a value proportional to a total quantity of the cells of the codeword, determine the cell metric for which the determined second derivative value has a greatest value, input the determined cell metric to a Pearson detector, and determine originally programmed data of the codeword using the Pearson detector.

    Erase method of non-volatile memory device
    9.
    发明授权
    Erase method of non-volatile memory device 有权

    公开(公告)号：US11783900B2

    公开(公告)日：2023-10-10

    申请号：US17840021

    申请日：2022-06-14

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Sang-Won Park ,  Won Bo Shim ,  Bong Soon Lim

    IPC: G11C16/16 ,  G11C16/24 ,  G11C16/34 ,  G11C16/12

    CPC classification number: G11C16/16 ,  G11C16/12 ,  G11C16/24 ,  G11C16/3445

    Abstract: A non-volatile memory device includes a memory cell array including a plurality of cell strings, each of the plurality of cell strings includes a gate-induced drain leakage (GIDL) transistor and a memory cell group, and a control logic to apply a voltage to each of the plurality of cell strings. The control logic performs a first erase operation of erasing the memory cell groups of each of the plurality of cell strings, a first verification operation of detecting erase results of the memory cell groups of each of the plurality of cell strings, and a program operation of programming the GIDL transistors of some of the plurality of cell strings.

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