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    Adaptive error avoidance in the memory devices
    2.
    发明授权
    Adaptive error avoidance in the memory devices 有权

    公开(公告)号：US12073905B2

    公开(公告)日：2024-08-27

    申请号：US17894528

    申请日：2022-08-24

    申请人： Micron Technology, Inc.

    发明人： Li-Te Chang ,  Yu-Chung Lien ,  Murong Lang ,  Zhenming Zhou ,  Michael G. Miller

    IPC分类号： G11C29/52 ,  G11C16/08 ,  G11C16/10 ,  G11C16/34

    CPC分类号： G11C29/52 ,  G11C16/08 ,  G11C16/102 ,  G11C16/3404

    摘要： An example method of performing memory access operations comprises: receiving a request to perform a memory access operation with respect to a set of memory cells connected to a wordline of a memory device; identifying a block family associated with the set of memory cells; determining, for each logical programming level of a plurality of logical programming levels, a corresponding default block family error avoidance (BFEA) threshold voltage offset value associated with the block family; determining a value of a data state metric associated with the set of memory cells; responsive to determining that the value of the data state metric satisfies a threshold criterion, determining, for each logical programming level of a plurality of logical programming levels, a corresponding sub-BFEA threshold voltage offset value; and performing the memory access operation by applying, for each logical programming level of the plurality of logical programming levels, a combination of the default BFEA threshold voltage value, the sub-BFEA threshold voltage value, and a corresponding base voltage level.

    Performing data integrity checks to identify defective wordlines
    3.
    发明授权
    Performing data integrity checks to identify defective wordlines 有权

    公开(公告)号：US12062394B2

    公开(公告)日：2024-08-13

    申请号：US17546425

    申请日：2021-12-09

    申请人： Micron Technology, Inc.

    发明人： Jian Huang ,  Zhenming Zhou

    IPC分类号： G11C16/10 ,  G11C16/08 ,  G11C16/26 ,  G11C29/44 ,  G11C29/12

    CPC分类号： G11C16/102 ,  G11C16/08 ,  G11C16/26 ,  G11C29/4401 ,  G11C2029/1202

    摘要： Systems and methods are disclosed including a memory device and a processing device operatively coupled to the memory device. The processing device can perform operations comprising performing a write operation to program first data to a first set of memory cells addressable by a first wordline of a first plurality of wordlines of a block of the memory device; performing a read operation on a second wordline of the plurality of wordlines, wherein the second wordline is adjacent to the first wordline; determining a number of bits programmed in a first logical level in the second wordline; and responsive to determining that the number of bits set satisfies a threshold criterion, copying second data from the first block to a second block.

    SELECTIVE DATA PATTERN WRITE SCRUB FOR A MEMORY SYSTEM
    5.
    发明公开
    SELECTIVE DATA PATTERN WRITE SCRUB FOR A MEMORY SYSTEM 审中-公开

    公开(公告)号：US20240233843A1

    公开(公告)日：2024-07-11

    申请号：US18425383

    申请日：2024-01-29

    申请人： MICRON TECHNOLOGY, INC.

    发明人： Zhongguang Xu ,  Murong Lang ,  Zhenming Zhou

    IPC分类号： G11C16/34

    CPC分类号： G11C16/3495 ,  G11C16/3404

    摘要： A system includes a memory device having a plurality of memory cells and a processing device operatively coupled to the memory device. The processing device is to determine to perform a rewrite on at least a portion of the plurality of memory cells. The processing device can determine that a number of rewrite operations at first subset of memory cells storing a first logic state fail to satisfy a threshold criterion. The processing device can also cause a rewrite of data stored at a second subset of memory cells storing a second logic state in response to determining the number of rewrite operations performed at the first subset of memory cells fail to satisfy the threshold criterion.

    PASS VOLTAGE ADJUSTMENT FOR PROGRAM OPERATION IN A MEMORY DEVICE
    7.
    发明公开
    PASS VOLTAGE ADJUSTMENT FOR PROGRAM OPERATION IN A MEMORY DEVICE 审中-公开

    公开(公告)号：US20240203513A1

    公开(公告)日：2024-06-20

    申请号：US18528178

    申请日：2023-12-04

    申请人： Micron Technology, Inc.

    发明人： Yu-Chung Lien ,  Zhenming Zhou

    IPC分类号： G11C16/34 ,  G11C16/10 ,  G11C29/02

    CPC分类号： G11C16/3459 ,  G11C16/102 ,  G11C16/3495 ,  G11C29/022

    摘要： A request to perform a program operation on a set of vertically stacked memory cells of a memory device is received. A pass voltage adjustment value based on a number of program erase cycles (PECs) associated with the memory device is determined responsive to determining that at least one memory cell of the set of vertically stacked memory cells is non-programmable. A default pass voltage is adjusted by the pass voltage adjustment value to generate an adjusted pass voltage. The program operation on the set of vertically stacked memory cells is performed using the adjusted pass voltage.

    Selective data pattern write scrub for a memory system
    8.
    发明授权
    Selective data pattern write scrub for a memory system 有权

    公开(公告)号：US11929127B2

    公开(公告)日：2024-03-12

    申请号：US17463207

    申请日：2021-08-31

    申请人： MICRON TECHNOLOGY, INC.

    发明人： Zhongguang Xu ,  Murong Lang ,  Zhenming Zhou

    IPC分类号： G11C16/34

    CPC分类号： G11C16/3495 ,  G11C16/3404

    摘要： A system includes a memory device having a plurality of memory cells and a processing device operatively coupled to the memory device. The processing device is to determine to perform a rewrite on at least a portion of the plurality of memory cells. The processing device can determine that a number of rewrite operations at first subset of memory cells storing a first logic state fail to satisfy a threshold criterion. The processing device can also cause a rewrite of data stored at a second subset of memory cells storing a second logic state in response to determining the number of rewrite operations performed at the first subset of memory cells fail to satisfy the threshold criterion.